TF50N02 TUOFENG | Alldatasheet

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Technical content

Description

  • High density cell design for ultra low Rdson
  • Fully characterized avalanche voltage and current
  • Excellent package for good heat dissipation Application
  • Power switching application
  • Hard switched and high frequency circuits
  • Uninterruptible power supply D G S Schematic diagram Absolute Maximum Ratings (TA =25℃℃ ℃℃unless otherwise noted) Parameter Symbol Limit Unit Drain-Source Voltage VDS Gate-Source Voltage VGS Drain Current-Continuous ID Drain Current-Pulsed (Note 1) IDM Maximum Power Dissipation PD 30 W Operating Junction and Storage Temperature Range TJ,TSTG -55 To 150 ℃ Thermal Characteristic Thermal Resistance,Junction-to-Ambient (Note 2) R θJA /W℃ Electrical Characteristics (TA =25℃unless otherwise noted) Parameter Symbol Condition Min Typ Max Unit Off Characteristics Drain-Source Breakdown Voltage BV DSS V GS =0V ID =250µA - V A 500 n - - VDSS RDS(ON) @4.5V (typ) ID A Marking and pin Assignment TO -252 Shenzhen Tuofeng Semiconductor Technology Co., Ltd N -CHANNEL ENHANCEMENT MODE POWER MOSFET A TFXXXYY TF50N02 The TF50N0 2 TO-252 uses advanced trench technology and design to provide excellent RDS(ON) with low gate charge. It can be used in a wide variety of applications. 50N0250A 20V 5.1mΩ 20 V 150 2.1 ±12 V Zero Gate Voltage Drain Current I DSS V DS =20V, VGS =0V 20 23 www.tuofeng.com Feb,2021 V1.0

On Characteristics (Note 3) Drain-Source On-State Resistance R DS(ON) Ω Dynamic Characteristics (Note4) Input Capacitance C lss - PF Output Capacitance C oss - PF Reverse Transfer Capacitance C rss Switching Characteristics (Note 4) Turn-on Delay Time t d(on) Turn-on Rise Time t r 5.2 Turn-Off Delay Time t d(off) Turn-Off Fall Time t f Total Gate Charge Q g 11 nC Gate-Source Charge Q gs Gate-Drain Charge Q gd Drain-Source Diode Characteristics Diode Forward Current (Note 2) I S Notes: 1. Repetitive Rating: Pulse width limited by maximum junction temperature. 2. Surface Mounted on FR4 Board, t ≤ 10 sec. 3. Pulse Test: Pulse Width ≤ 300µs, Duty Cycle ≤ 2%. 4. Guaranteed by design, not subject to production m V - - ±100 nA - - 10 A S - PF - nS 18 - nS 6.0 - nS - 11.7 - nS - - - 2.2 nC - - 4.2 nC - - Shenzhen Tuofeng Semiconductor Technology Co., Ltd N -CHANNEL ENHANCEMENT MODE POWER MOSFET TF50N02 Gate-Body Leakage Current I GSS V GS =±12V,VDS =0V 0.7 1.0 0.5 5.1 8.0 116.9 Forward Transconductance g FS V DS =5V,ID =10A VGS=2.5V, ID=12A Gate Threshold Voltage V GS(th) V DS =VGS ,ID =250µA VGS=4.5V, ID=18A VDS =10V,VGS =0V, F=1.0MHz VDD =10V,ID =1.0A VGS =10V,RG =6.0Ω VDS =10V,ID =5A, VGS =10V 279 273 1500 Diode Forward Voltage (Note 3) V SD V GS =0V,IS=20A - 0.8 1. 2 V www.tuofeng.com Feb,2021 V1.0

1）EAS test Circuits 2）Gate charge test Circuit: 3）Switch Time Test Circuit： Shenzhen Tuofeng Semiconductor Technology Co., Ltd N -CHANNEL ENHANCEMENT MODE POWER MOSFET TF50N02 www.tuofeng.com Feb,2021 V1.0

Package Information

UNIT: mm 0.25 GAUGE PLANE L VIEW A SEATING PLANE L4 L3D E e H A SEE VIEW A b c SYMBOL MIN. MAX. 2.39 4.95 5.46 0.46 0.61 0.13 5.33 A c D E MILLIMETERS b 0.50 0.89

2.29 BSC

4.57 6.35 6.73 6.22

0.090 BSC

MIN. MAX. INCHES 0.094 0.020 0.035 0.195 0.215 0.018 0.024 0.210 0.180 0.250 0.265 2.18 0.245 0.086 0.005 0.035 0.070 0.410 H L e 9.40 0.90 0.46 0.89 1.78 10.41 0.370 0.035 0.018 0.040L4 1.02 0.1503.81 0.89 2.03 0.035 0.080 0 8°0° 8°0° 6.00 6.00 0.236 0.236 6.8 MIN. 3 MIN. 6.25 MIN. 6.6 1.5 MIN. 2.286 4.572 Shenzhen Tuofeng Semiconductor Technology Co., Ltd N -CHANNEL ENHANCEMENT MODE POWER MOSFET TF50N02