Z1212A

AOZ1212 AOSMD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 18

Technical content

Features

• 4.5V to 27V operating input voltage range
• 70mΩ internal NFET, efficiency: up to 95%
• Internal soft start
• Output voltage adjustable down to 0.8V
• 3A continuous output current
• Fixed 370kHz PWM operation
• Cycle-by-cycle current limit
• Short-circuit protection
• Thermal shutdown
• Small size SO-8 or DFN-8 package

Applications

• Point of load DC/DC conversion
• Set top boxes
• DVD drives and HDD
• LCD monitors and TVs
• Cable modems
• Telecom/networking/datacom equipment Typical Application

Figure 1. 3.3V/3A Buck Regulator

Rev. 1.7 November 2010 www.aosmd.com Page 2 of 18

Ordering Information

AOS Green Products use reduced levels of Halogens, and are also RoHS compliant. Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information. Pin Configuration Pin Description Part Number Ambient Temperature Range Package Environmental AOZ1212AI -40°C to +85°C SO-8 RoHS Compliant Green ProductAOZ1212DI -40°C to +85°C 5 x 4 DFN-8 VBIAS VIN EN COMP LX BST GND FB SO-8 (Top View) DFN-8 (Top Thru View) VBIAS VIN EN COMP LX BST GND FB VIN GND Pin Number Pin Name Pin Function 1 LX PWM output connection to inductor. LX pin needs to be connected externally. Thermal connection for output stage. 2 BST Bootstrap voltage input. High side driver s upply. Connected to 0.1µF capacitor between BST and LX. 3 GND Ground. 4 FB Feedback input. It is regulated to 0.8V. The FB pin is used to determine the PWM output voltage via a resistor divider between the output and GND. 5 COMP External loop compensation. Output of internal error amplifier. Connect a series RC network to GND for control loop compensation. 6 EN Enable pin. The enable pin is active HIGH. Connect EN pin to V IN if not used. Do not leave the EN pin floating. 7V IN Supply voltage input. Range from 4.5V to 27V. When VIN rises above the UVLO threshold the device starts up. All VIN pins need to be connected externally. 8 VBIAS Compensation pin of internal linear regulator. Place put a 1µF capacitor between this pin and ground.

Rev. 1.7 November 2010 www.aosmd.com Page 3 of 18 Block Diagram Absolute Maximum Ratings Exceeding the Absolute Maximum Ratings may damage the device. Note: 1. Devices are inherently ESD sensitive, handling precautions are required. Human body model rating: 1.5kΩ in series with 100pF. Recommended Operating Conditions The device is not guaranteed to operate beyond the Recom- mended Operating Conditions. Note: 2. The value of ΘJA is measured with the device mounted on 1-in2 FR-4 board with 2oz. Copper, in a still air environment with TA = 25°C. The value in any given application depends on the user's spe- cific board design. 370kHz/24kHz Oscillator GND VIN EN VBIAS FB COMP LX BST OTP ILimit PWM Control Logic 5V LDO Regulator UVLO & POR +5V GM = 200µA/V SoftstartReference & Bias 0.8V PWM Comp ISen EAmp 0.2V Frequency Foldback Comparator Parameter Rating Supply Voltage (VIN) 30V LX to GND -0.7V to V IN+0.3V EN to GND -0.3V to V IN+0.3V FB to GND -0.3V to 6V COMP to GND -0.3V to 6V BST to GND V LX+6V VBIAS to GND -0.3V to 6V Junction Temperature (T J) +150°C Storage Temperature (TS) -65°C to +150°C ESD Rating: Human Body Model(1) 2kV Parameter Rating Supply Voltage (VIN) 4.5V to 27V Output Voltage Range 0.8V to 0.85*V IN Ambient Temperature (TA) -40°C to +85°C Package Thermal Resistance (ΘJA)(2) SO-8 DFN-8 105°C/W 53°C/W

Rev. 1.7 November 2010 www.aosmd.com Page 4 of 18

Electrical Characteristics

TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified(3) Note: 3. Specification in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are guaranteed by design. Symbol Parameter Conditions Min. Typ. Max. Units VIN Supply Voltage 4.5 27 V VUVLO Input Under-Voltage Lockout Threshold V IN Rising VIN Falling 4.3 4.1 V IIN Supply Current (Quiescent) I OUT = 0, VFB = 1.2V, VEN > 2V 23 mA IOFF Shutdown Supply Current V EN = 0V 32 0 µA VFB Feedback Voltage 0.782 0.8 0.818 V Load Regulation 0.5 % Line Regulation 0.08 % / V I FB Feedback Voltage Input Current 200 nA ENABLE VEN EN Input Threshold Off Threshold On Threshold 2.5 0.6 V VHYS EN Input Hysteresis 200 mV IEN Enable Sink/Source Current 50 nA MODULATOR fO Frequency 315 370 425 kHz DMAX Maximum Duty Cycle 85 % DMIN Minimum Duty Cycle 6% GVEA Error Amplifier Voltage Gain 500 V / V GEA Error Amplifier Transconductance 200 µA / V PROTECTION ILIM Current Limit 4.0 6.0 A Over-Temperature Shutdown Limit T J Rising TJ Falling 145 100 °C fSC Short Circuit Hiccup Frequency V FB = 0V 24 kHz tSS Soft Start Interval 6m s PWM OUTPUT STAGE RDS(ON) High-Side Switch On-Resistance 70 100 m Ω High-Side Switch Leakage V EN = 0V, VLX = 0V 10 µA

Rev. 1.7 November 2010 www.aosmd.com Page 5 of 18 Typical Performance Characteristics Circuit of Figure 1. TA = 25°C, VIN = VEN = 24V, VOUT = 3.3V unless otherwise specified. Light Load (DCM) Operation Full Load (CCM) Operation Startup to Full Load Short Circuit Protection 50% to 100% Load Transient Short Circuit Recovery 1μs/div 1 μs/div 2ms/div 200 μs/div 200μs/div 2ms/div Vin ripple 0.1V/div Vo ripple 20mV/div Vo 2V/div lin 0.5A/div Vo Ripple 200mV/div lo 1A/div Vo 2V/div lL 2A/div Vo 2V/div IL 2A/div IL 1A/div VLX 20V/div Vin ripple 0.1V/div Vo ripple 20mV/div IL 1A/div VLX 20V/div

Rev. 1.7 November 2010 www.aosmd.com Page 6 of 18 Efficiency Curves Efficiency VIN = 5V 1.8V OUTPUT 5.0V OUTPUT 5.0V OUTPUT 3.3V OUTPUT 3.3V OUTPUT 8.0V OUTPUT 8.0V OUTPUT 3.3V OUTPUT 100 Current (A) Efficieny (%) Efficiency VIN = 12V 100 Current (A) Efficieny (%) Efficiency VIN = 24V 100 Current (A) Efficieny (%)

Rev. 1.7 November 2010 www.aosmd.com Page 7 of 18 Detailed Description The AOZ1212 is a current-mode step down regulator with integrated high side NMOS switch. It operates from a 4.5V to 27V input voltage range and supplies up to 3A of load current. The duty cycle can be adjusted from 6% to 85% allowing a wide range of output voltages. Fea- tures include enable control, Power-On Reset, input under voltage lockout, fixed internal soft-start and ther- mal shut down. The AOZ1212 is available in an SO-8 or DFN-8 package. Enable and Soft Start The AOZ1212 has an internal soft start feature to limit in-rush current and ensure the output voltage ramps up smoothly to the regulation voltage. A soft start process begins when the input voltage rises to 4.1V and voltage on EN pin is HIGH. In the soft start process, the output voltage is typically ramped to regulation voltage in 6.8ms. The 6.8ms soft start time is set internally. If the enable function is not used, connect the EN pin to V IN. Pulling EN to ground will disable the AOZ1212. Do not leave EN open. The voltage on the EN pin must be above 2.5 V to enable the AOZ1212. When voltage on EN pin falls below 0.6V, the AOZ1212 is disabled. If an application circuit requires the AOZ1212 to be disabled, an open drain or open collector circuit should be used to interface with the EN pin. Steady-State Operation Under steady-state conditions, the converter operates in fixed frequency and Continuous-Conduction Mode (CCM). The AOZ1212 integrates an internal N-MOSFET as the high-side switch. Inductor current is sensed by amplifying the voltage drop across the drain to source of the high side power MOSFET. Since the N-MOSFET requires a gate voltage higher than the input voltage, a boost capacitor connected between the LX and BST pins drives the gate. The boost capacitor is charged while LX is low. An internal 10 Ω switch from LX to GND is used to ensure that LX is pulled to GND even in the light load. Output voltage is divided down by the external voltage divider at the FB pin. The difference of the FB pin voltage and reference is amplified by the internal transconductance error amplifier. The error voltage, which shows on the COMP pin, is compared against the current signal. The current signal is the sum of inductor current signal and ramp compensation signal, at the PWM comparator input. If the current signal is less than the error voltage, the internal high-side switch is on. The inductor current flows from the input through the inductor to the output. When the current signal exceeds the error voltage, the high-side switch is off. The inductor current is free- wheeling through the Schottky diode to the output. Switching Frequency The AOZ1212 switching frequency is fixed and set by an internal oscillator. The switching frequency is set to 370kHz. Output Voltage Programming Output voltage can be set by feeding back the output to the FB pin with a resistor divider network. In the applica- tion circuit shown in Figure 1. The resistor divider network includes R 1 and R2. Typically, a design is started by picking a fixed R2 value and calculating the required R1 value with equation below. Some standard values for R1 and R2 for the most commonly used output voltages are listed in Table 1. Table 1. The combination of R1 and R2 should be large enough to avoid drawing excessive current from the output, which will cause power loss. Protection Features The AOZ1212 has multiple protection features to prevent system circuit damage under abnormal conditions. Over Current Protection (OCP) The sensed inductor current signal is also used for over current protection. Since the AOZ1212 employs peak current mode control, the COMP pin voltage is propor- tional to the peak inductor current. The COMP pin volt- age is limited to be between 0.4V and 2.5V internally. The peak inductor current is automatically limited cycle by cycle. The cycle-by-cycle current limit threshold is internally set. When the load current reaches the current limit thresh- old, the cycle-by-cycle current limit circuit turns off the VO (V) R1 (kΩ) R2 (kΩ) 0.8 1.0 Open 1.2 4.99 10 1.5 10 11.5 1.8 12.7 10.2 2.5 21.5 10 3.3 31.6 10 5.0 52.3 10 VO 0.8 1 ⎛⎞×=

Rev. 1.7 November 2010 www.aosmd.com Page 9 of 18 The peak inductor current is: High inductance gives low inductor ripple current but requires larger size inductor to avoid saturation. Low ripple current reduces inductor core losses. It also reduces RMS current through inductor and switches, which results in less conduction loss. When selecting the inductor, make sure it is able to handle the peak current without saturation even at the highest operating temperature. The inductor takes the highest current in a buck circuit. The conduction loss on inductor needs to be checked for thermal and efficiency requirements. Surface mount inductors in different shape and styles are available from Coilcraft, Elytone and Murata. Shielded inductors are small and radiate less EMI noise. But they cost more than unshielded inductors. The choice depends on EMI requirement, price and size. Output Capacitor The output capacitor is selected based on the DC output voltage rating, output ripple voltage specification and ripple current rating. The selected output capacitor must have a higher rated voltage specification than the maximum desired output voltage including ripple. De-rating needs to be consid- ered for long term reliability. Output ripple voltage specification is another important factor for selecting the output capacitor. In a buck con- verter circuit, output ripple voltage is determined by inductor value, switching frequency, output capacitor value and ESR. It can be calculated by the equation below: where; CO is output capacitor value and ESRCO is the Equivalent Series Resistor of output capacitor. When low ESR ceramic capacitor is used as output capacitor, the impedance of the capacitor at the switch- ing frequency dominates. Output ripple is mainly caused by capacitor value and inductor ripple current. The output ripple voltage calculation can be simplified to: If the impedance of ESR at switching frequency dominates, the output ripple voltage is mainly decided by capacitor ESR and inductor ripple current. The output ripple voltage calculation can be further simplified to: For lower output ripple voltage across the entire operat- ing temperature range, X5R or X7R dielectric type of ceramic, or other low ESR tantalum capacitor or aluminum electrolytic capacitor may also be used as out- put capacitors. In a buck converter, output capacitor current is continu- ous. The RMS current of output capacitor is decided by the peak to peak inductor ripple current. It can be calcu- lated by: Usually, the ripple current rating of the output capacitor is a smaller issue because of the low current stress. When the buck inductor is selected to be very small and induc- tor ripple current is high, output capacitor could be over- stressed. Schottky Diode Selection The external freewheeling diode supplies the current to the inductor when the high side NMOS switch is off. To reduce the losses due to the forward voltage drop and recovery of diode, a Schottky diode is recommended. The maximum reverse voltage rating of the chosen Schottky diode should be greater than the maximum input voltage, and the current rating should be greater than the maximum load current. Loop Compensation The AOZ1212 employs peak current mode control for easy use and fast transient response. Peak current mode control eliminates the double pole effect of the output L&C filter. It greatly simplifies the compensation loop design. With peak current mode control, the buck power stage can be simplified to be a one-pole and one-zero system in frequency domain. The pole is the dominant pole and can be calculated by: ILpeak IO ΔIL ΔVO ΔIL ESR CO 8 fC O×× ⎛⎞×= ΔVO ΔIL 8 fC O×× ⎛⎞×= ΔVO ΔIL ESR CO×= ICO_RMS ΔIL fp1 2π CO RL××

Rev. 1.7 November 2010 www.aosmd.com Page 10 of 18 The zero is a ESR zero due to output capacitor and its ESR. It is can be calculated by: where; CO is the output filter capacitor, RL is load resistor value, and ESRCO is the equivalent series resistance of output capacitor. The compensation design is actually to shape the converter close loop transfer function to get desired gain and phase. Several different types of compensation network can be used for AOZ1212. For most cases, a series capacitor and resistor network connected to the COMP pin sets the pole-zero and is adequate for a stable high-bandwidth control loop. In the AOZ1212, FB pin and COMP pin are the inverting input and the output of internal transconductance error amplifier. A series R and C compensation network connected to COMP provides one pole and one zero. The pole is: where; GEA is the error amplifier transconductance, which is 200 x 10-6 A/V, GVEA is the error amplifier voltage The zero given by the external compensation network, capacitor CC (C5 in Figure 1) and resistor RC (R1 in Figure 1), is located at: To design the compensation circuit, a target crossover frequency fC for close loop must be selected. The system crossover frequency is where the control loop has unity gain. The crossover frequency is also called the converter bandwidth. Generally a higher bandwidth means faster response to load transient. However, the bandwidth should not be too high due to system stability concern. When designing the compensation loop, converter stability under all line and load condition must be considered. Usually, it is recommended to set the bandwidth to be less than 1/10 of switching frequency. It is recommended to choose a crossover frequency less than 30kHz. The strategy for choosing R C and CC is to set the cross over frequency with RC and set the compensator zero with CC. Using selected crossover frequency, fC, to calculate RC: where; fC is desired crossover frequency, VFB is 0.8V, GEA is the error amplifier transconductance, which is 200x10-6 A/V, and GCS is the current sense circuit transconductance, which is

5.64 A/V

The compensation capacitor CC and resistor RC together make a zero. This zero is put somewhere close to the dominate pole fp1 but lower than 1/5 of the selected crossover frequency. C C can is selected by: The equation above can also be simplified to: An easy-to-use application software which helps to design and simulate the compensation loop can be found at www.aosmd.com Thermal Management and Layout Consideration In the AOZ1212 buck regulator circuit, high pulsing current flows through two circuit loops. The first loop starts from the input capacitors, to the V IN pin, to the LX pins, to the filter inductor, to the output capacitor and load, and then returns to the input capacitor through ground. Current flows in the first loop when the high side switch is on. The second loop starts from inductor, to the output capacitors and load, to the GND pin of the AOZ1212, to the LX pins of the AZO1212. Current flows in the second loop when the low side diode is on. In PCB layout, minimizing the two loops area reduces the noise of this circuit and improves efficiency. A ground plane is recommended to connect input capacitor, output capacitor, and GND pin of the AOZ1212. In the AOZ1212 buck regulator circuit, the three major power dissipating components are the AOZ1212, external diode and output inductor. The total power fZ1 2π CO ESR CO×× fp2 GEA 2π CC GVEA×× fZ2 2π CC RC×× fC 30kHz= RC fC VO VFB 2π CO× GEA GCS× CC 1.5 2π RC fp1×× CC CO RL× RC

Rev. 1.7 November 2010 www.aosmd.com Page 11 of 18 dissipation of converter circuit can be measured by input power minus output power. The power dissipation of inductor can be approximately calculated by output current and DCR of the inductor. The power dissipation of the diode is: The actual AOZ1212 junction temperature can be calculated with power dissipation in the AOZ1212 and thermal impedance from junction to ambient. The maximum junction temperature of AOZ1212 is 145°C, which limits the maximum load current capability. The thermal performance of the AOZ1212 is strongly affected by the PCB layout. Care should be taken by users during design process to ensure that the IC will operate under the recommended environmental conditions. Several layout tips are listed below for the best electric and thermal performance. Figure 3a and Figure 3b show layout examples for the AOZ1212A and AOZ1212D respectively. 1. Do not use thermal relief connection to the V IN and the GND pin. Pour a maximized copper area to the GND pin and the V IN pin to help thermal dissipation. 2. Input capacitor should be connected as close as possible to the VIN and GND pins. 3. Make the current trace from LX pins to L to C O to GND as short as possible. 4. Pour copper plane on all unused board area and connect it to stable DC nodes, like VIN, GND or VOUT. 5. Keep sensitive signal traces such as the trace connecting FB and COMP pins away from the LX pins. Ptotal_loss VIN IIN VO IO×–×= Pinductor_loss IO 2 Rinductor 1.1××= Pdiode_loss IO VF 1 VO VIN ⎛⎞××= T junction Ptotal_loss Pinductor_loss–() Θ × JA= Tambient++

Rev. 1.7 November 2010 www.aosmd.com Page 12 of 18 Figure 3a. Layout Example for AOZ1212AI Figure 3b. Layout Example for AOZ1212DI AOZ1210 /2

3 GND

2 BST

1 L X

7 Vin

8 VBIAS

5 COMP

Rev. 1.7 November 2010 www.aosmd.com Page 13 of 18 Package Dimensions, SO-8 Notes: 1. All dimensions are in millimeters. 2. Dimensions are inclusive of plating 3. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 6 mils. 4. Dimension L is measured in gauge plane. 5. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact. Symbols A b c D e E h L θ Dimensions in millimeters Min. 1.35 0.10 1.25 0.31 0.17 4.80 3.80 5.80 0.25 0.40 D C L h x 45° 7° (4x) b 2.20 5.74 0.80 Unit: mm 1.27 A2 A 0.1 θ Gauge Plane Seating Plane 0.25e E1E Nom. 1.65 1.50 4.90 3.90

1.27 BSC

6.00 Max. 1.75 0.25 1.65 0.51 0.25 5.00 4.00 6.20 0.50 1.27 Symbols A b c D e E h L θ Dimensions in inches Min. 0.053 0.004 0.049 0.012 0.007 0.189 0.150 0.228 0.010 0.016 Nom. 0.065 0.059 0.193 0.154

0.050 BSC

0.236 Max. 0.069 0.010 0.065 0.020 0.010 0.197 0.157 0.244 0.020 0.050

Rev. 1.7 November 2010 www.aosmd.com Page 14 of 18 Tape and Reel Dimensions, SO-8 SO-8 Carrier Tape SO-8 Reel SO-8 Tape Leader/Trailer & Orientation Tape Size 12mm Reel Size ø330 M ø330.00 ±0.50 Package SO-8 (12mm) 6.40 ±0.10 5.20 ±0.10 2.10 ±0.10 1.60 ±0.10 1.50 ±0.10 E 12.00 ±0.10 1.75 ±0.10 5.50 ±0.10 8.00 ±0.10 4.00 ±0.10 2.00 ±0.10 T 0.25 ±0.10 N ø97.00 ±0.10 Unit: mm G M S K H N W V R Trailer Tape 300mm min. or 75 empty pockets Components Tape Orientation in Pocket Leader Tape 500mm min. or 125 empty pockets See Note 5 See Note 3 See Note 3 Feeding DirectionP0 E T W 13.00 ±0.30 17.40 ±1.00 H ø13.00 +0.50/-0.20 K 10.60 S 2.00 ±0.50 G R V

Rev. 1.7 November 2010 www.aosmd.com Page 15 of 18 Package Dimensions, 5x4A DFN-8 Notes: 1. Dimensions and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters. 3. The location of the terminal #1 identifier and terminal numbering convention conforms to JEDEC publication 95 SP-002. 4. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension b should not be measured in that radius area. 5. Coplanarity applies to the terminals and all other bottom surface metallization. 6. Drawing shown are for illustration only. 7. The dimensions with * are just for reference 8. Pin #3 and Pin #7 are fused to DAP. Symbols A b D E e L R aaa bbb ccc ddd eee Dimensions in millimeters RECOMMENDED LAND PATTERN FRONT VIEW TOP VIEW BOTTOM VIEW BOTTOM VIEW Min. 0.70 0.40 4.90 2.05 1.66 3.90 2.23 0.50 Nom. 0.75 0.20 Ref. 0.45 5.00 2.15 1.76 4.00 2.33

0.95 BSC

0.55 0.40 0.285 Ref. 0.835 Ref. 0.30 Ref. 0.15 0.10 0.10 0.08 0.05 Max. 0.80 0.50 5.10 2.25 1.86 4.10 2.43 0.60 Symbols A b D E e L R aaa bbb ccc ddd eee Min. 0.028 0.016 0.190 0.080 0.064 0.154 0.088 0.020 Nom. 0.30 0.008 Ref. 0.018 0.200 0.085 0.070 0.157 0.092

0.037 BSC

0.022 0.016 0.011 Ref. 0.033 Ref. 0.012 Ref. 0.006 0.004 0.004 0.003 0.002 Max. 0.032 0.020 0.201 0.089 0.074 0.161 0.096 0.024 4.51 0.285 2.331.165 0.285 1.86 0.40 2.25 0.50 Typ. 0.95 Typ. 0.65 4.20 Dimensions in inches b A Seating Plane D/2 E/2 D E L L2* L3* L2* e D2 Chamfer 0.30 Pin #1 IDA Option 1 Index Area (D/2 x E/2) Pin #1 IDA Option 2 R

Rev. 1.7 November 2010 www.aosmd.com Page 16 of 18 Tape and Reel Dimensions, 5x4A DFN-8 R0.40 P0K0 A0 E E2 D0 Package DFN 5x4 (12 mm) A0 B0 K0 E E1 E2 D0 D1 P0 P1 P2 T 5.30 ±0.10 ±0.10 4.30 ±0.10 1.20 Min. 1.50 1.50 12.00 ±0.10 1.75 ±0.10 5.50 ±0.10 8.00 ±0.20 4.00 ±0.10 2.00 ±0.05 0.30 UNIT: mm T Typ. 0.20 Feeding Direction Tape Leader/Trailer and Orientation ±0.30+0.10 / –0 Trailer Tape 300mm Min. Components Tape Orientation in Pocket Leader Tape 500mm Min.

Rev. 1.7 November 2010 www.aosmd.com Page 17 of 18 Reel VIEW: C C 0.05 3-1.8 ø96 ±0.2 6.45±0.05 3-ø2. 9±0.05 3-ø 1/8" 3-ø1 /4" 8.9±0.1 11.90

14 REF

1.8 5.0

12 REF

41.5 REF

43.00 44.5±0.1 2.00 6.50 10.0 10.71 10° 3-ø3/1 R48 REF ø86.0 ±0.1 2.20 6.2 ø13.00 ø21.20 ø17.0 R1.10 R3.10 2.00 3.3 4.0 6.10 0.80 3.00 8.00 +0.05 0.00 R0.5 1.80 2.5 38° 44.5±0.1 46.0±0.1 8.0±0.1 40° 3-ø3/16" R3.956.50 ø90.00 6.01.8 1.8 8.00 0.00 -0.05 N=ø100±2 A A A R121 R127 P B M II I I 6.0±1 Zoom In III Zoom In II Zoom In A Tape Size 12mm Reel Size ø330 M ø330 +0.3 -4.0 12.40 +2.0 -0.0 B 2.40 ±0.3 P 0.5

Rev. 1.7 November 2010 www.aosmd.com Page 18 of 18 As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. This data sheet contains preliminary data; supplementary data may be published at a later date. Alpha & Omega Semiconductor reserves the right to make changes at any time without notice. LIFE SUPPORT POLICY ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. Part Marking AOZ1212AI AOZ1212DI Z1212AI FAY Part Number Assembly Lot CodeFab & Assembly Location Year & Week Code WLT Z1212DI FAY Part Number Assembly Lot CodeFab & Assembly Location Year & Week Code WLT