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Technical content
Features
z 4.5 V to 18 V operating input voltage range z Synchronous Buck: 70 mΩ internal high-side switch and 40 mΩ internal low-side switch (at 12 V) z Up to 95 % efficiency z External soft start z Output voltage adjustable to 0.8 V z 3 A continuous output current z 500 kHz PWM operation z Cycle-by-cycle current limit z Pre-bias start-up z Short-circuit protection z Thermal shutdown z Exposed pad SO-8 package
Applications
z Point of load DC/DC converters z LCD TV z Set top boxes z DVD and Blu-ray players/recorders z Cable modems Typical Application Figure 1. 3.3 V 3 A Synchronous Buck Regulator, Fs = 500 kHz
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Ordering Information
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant. Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information. Pin Configuration Pin Description Part Number Ambient Temperature Range Package Environmental AOZ1051PI -40 °C to +85 °C EPAD SO-8 Green Product PGND VIN AGND FB Exposed Pad SO-8 (Top View) PAD (LX) NC SS EN COMP Pin Number Pin Name Pin Function 1 PGND Power ground. PGND needs to be electrically connected to AGND. 2 VIN Supply voltage input. When VIN rises above the UVLO threshold and EN is logic high, the device starts up. 3 AGND Analog ground. AGND is the reference point for controller section. AGND needs to be electrically connected to PGND. 4 FB Feedback input. The FB pin is used to set t he output voltage via a resistive voltage divider between the output and AGND. 5 COMP External loop compensation pin. Conne ct a RC network between COMP and AGND to compensate the control loop. 6 EN Enable pin. Pull EN to logic high to enable the device. Pull EN to logic low to disable the device. If on/off control in not needed, connect EN to VIN and do not leave it open. 7 SS Soft-start pin. 5 µA current charging current. 8 NC No Connect Pin. Pin 8 is not internally con nected. Connect this pin externally to LX and use it for better thermal performance. Exposed pad LX Switching node. LX is t he drain of the internal PFET. LX is used as the thermal pad of the power stage.
Rev. 1.0 June 2011 www.aosmd.com Page 3 of 14 Block Diagram Absolute Maximum Ratings Exceeding the Absolute Maximum Ratings may damage the device. Note: 1. Devices are inherently ESD sensitive, handling precautions are required. Human body model rating: 1.5 kΩ in series with 100 pF. Recommended Operating Conditions The device is not guaranteed to operate beyond the Maximum Recommended Operating Conditions. Note: 2. The value of ΘJA is measured with the device mounted on a 1-in2 FR-4 board with 2 oz. Copper, in a still air environment with TA = 25 °C. The value in any given application depends on the user’s specific board design. 500kHz Oscillator AGND PGND VIN EN FB SS COMP LX OTPInternal +5V ILimit PWM Control Logic 5V LDO Regulator UVLO & POR SoftstartReference & Bias 0.8V SS 5µA PWM Comp Level Shifter FET Driver ISen EAmp Parameter Rating Supply Voltage (VIN) 20 V LX to AGND -0.7 V to V IN+0.3 V LX to AGND (20 ns) -5 V to 22 V EN to AGND -0.3 V to V IN+0.3 V FB, SS, COMP to AGND -0.3 V to 6.0 V PGND to AGND -0.3 V to +0.3 V Junction Temperature (TJ) +150 °C Storage Temperature (TS) -65 °C to +150 °C ESD Rating(1) 2.0 kV Parameter Rating Supply Voltage (VIN) 4.5 V to 18 V Output Voltage Range 0.8 V to 0.85 • VIN Ambient Temperature (TA) -40 °C to +85 °C Package Thermal Resistance Exposed Pad SO-8 (ΘJA)(2) 50 °C/W
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Electrical Characteristics
TA = 25 °C, VIN = VEN = 12 V, VOUT = 3.3 V unless otherwise specified(3) Note: 3. Specification in BOLD indicate an ambient temperature range of -40 °C to +85 °C. These specifications are guaranteed by design. Symbol Parameter Conditions Min. Typ. Max. Units VIN Supply Voltage 4.5 18 V VUVLO Input Under-Voltage Lockout Threshold VIN Rising VIN Falling 4.1 3.7 V IIN Supply Current (Quiescent) I OUT = 0, VFB = 1.2 V, VEN > 2 V 1.6 2.5 mA IOFF Shutdown Supply Current V EN = 0 V 11 0 µA VFB Feedback Voltage T A = 25 °C 0.788 0.8 0.812 V Load Regulation 0.5 % Line Regulation 1% IFB Feedback Voltage Input Current 200 nA VEN EN Input Threshold Off Threshold On Threshold 2 0.6 V VHYS EN Input Hysteresis 100 mV EN Leakage Current 1 µA SS Time C SS = 16 nF 2 ms MODULATOR fO Frequency 400 500 600 kHz DMAX Maximum Duty Cycle 85 % TMIN Controllable Minimum On Time 150 ns Current Sense Transconductance 8 A / V Error Amplifier Transconductance 200 µA / V PROTECTION ILIM Current Limit 3.5 4.5 A Over-Temperature Shutdown Limit T J Rising TJ Falling 150 100 OUTPUT STAGE High-Side Switch On-Resistance V IN = 12 V VIN = 5 V 110 mΩ Low-Side Switch On-Resistance V IN = 12 V VIN = 5 V m Ω
Rev. 1.0 June 2011 www.aosmd.com Page 5 of 14 AOZ1051PI Typical Performance Characteristics Circuit of Figure 1. TA = 25 °C, VIN = VEN = 12 V, VOUT = 3.3 V unless otherwise specified. Light Load Operation 2µs/div Start Up to Full Load 2ms/div Full Load Operation 2µs/div Short Circuit Protection 20ms/div Short Circuit Recovery 20ms/div Vin ripple 0.5V/div Vo ripple 0.1V/div IL 2A/div VLX 10V/div Vin 5V/div Vo 2V/div lin 2A/div LVX 10V/div Vo 2V/div IL 2A/div VLX 10V/div Vo 2V/div IL 2A/div 50% to 100% Load Transient 100µs/div Vo 0.1V/div Io 2A/div Vin ripple 0.1V/div Vo ripple 0.1V/div IL 2A/div VLX 10V/div
Rev. 1.0 June 2011 www.aosmd.com Page 6 of 14 Efficiency Detailed Description The AOZ1051PI is a current-mode step down regulator with an integrated high-side PMOS switch and a low-side NMOS switch. The AOZ1051PI operates from a 4.5 V to
18 V input voltage range and supplies up to 3 A of load
current. Features include enable control, power-on reset, input under voltage lockout, output over voltage protection, external soft-start and thermal shut down. The AOZ1051PI is available in an exposed pad SO-8 package. Enable and Soft Start The AOZ1051PI has an external soft start feature to limit in-rush current and ensure the output voltage ramps up smoothly to regulation voltage. The soft start process begins when the input voltage rises to 4.1 V and voltage on the EN pin is HIGH. In the soft start process, the FB voltage is ramped to follow the voltage of the soft start pin until it reaches 0.8 V. The voltage of the soft-start pin is charged by an internal 5 µA current. The EN pin of the AOZ1051PI is active high. Connect the EN pin to VIN if the enable function is not used. Pulling EN to ground will disable the AOZ1051PI. Do not leave EN open. The voltage on the EN pin must be above 2 V to enable the AOZ1051PI. When the EN pin voltage falls below 0.6 V, the AOZ1051PI is disabled. Steady-State Operation Under heavy load steady-state conditions, the converter operates in fixed frequency and Continuous-Conduction Mode (CCM). The AOZ1051PI integrates an internal P-MOSFET as the high-side switch. Inductor current is sensed by amplifying the voltage drop across the drain to source of the high side power MOSFET. Output voltage is divided down by the external voltage divider at the FB pin. The difference of the FB pin voltage and reference voltage is amplified by the internal transconductance error amplifier. The error voltage, which shows on the COMP pin, is compared against the current signal, which is the sum of inductor current signal and ramp compensation signal, at the PWM comparator input. If the current signal is less than the error voltage, the internal high-side switch is on. The inductor current flows from the input through the inductor to the output. When the current signal exceeds the error voltage, the high-side switch is off. The inductor current is freewheeling through the internal low-side N-MOSFET switch to output. The internal adaptive FET driver guarantees no turn on overlap of both the high-side and the low-side switch. Efficiency (VIN = 12V) vs. Load Current 100 Load Current (A) Efficiency (%) 5V OUTPUT 3.3V OUTPUT 1.8V OUTPUT 1.2V OUTPUT
loss in the low-side switch. RDS(ON) is the on resistance of the internal MOSFET. Figure 1. The resistor divider network includes R1 and output voltages are listed in Table 1. voltage is limited to be between 0.4 V and 2.5 V internally. switching cycle because the output voltage is 0 V. converter will be shut down. temperature decreases to 100 ºC.
Rev. 1.0 June 2011 www.aosmd.com Page 9 of 14 Output Capacitor The output capacitor is selected based on the DC output voltage rating, output ripple voltage specification and ripple current rating. The selected output capacitor must have a higher rated voltage specification than the maximum desired output voltage including ripple. De-rating needs to be considered for long term reliability. Output ripple voltage specification is another important factor for selecting the output capacitor. In a buck converter circuit, output ripple voltage is determined by inductor value, switching frequency, output capacitor value and ESR. It can be calculated by the equation below: where, CO is output capacitor value, and ESRCO is the equivalent series resistance of the output capacitor. When a low ESR ceramic capacitor is used as the output capacitor, the impedance of the capacitor at the switching frequency dominates. Output ripple is mainly caused by capacitor value and inductor ripple current. The output ripple voltage calculation can be simplified to: If the impedance of ESR at switching frequency dominates, the output ripple voltage is mainly decided by capacitor ESR and inductor ripple current. The output ripple voltage calculation can be further simplified to: For lower output ripple voltage across the entire operating temperature range, X5R or X7R dielectric type of ceramic, or other low ESR tantalum capacitors are recommended as output capacitors. In a buck converter, output capacitor current is continuous. The RMS current of output capacitor is decided by the peak to peak inductor ripple current. It can be calculated by: Usually, the ripple current rating of the output capacitor is a smaller issue because of the low current stress. When the buck inductor is selected to be very small and inductor ripple current is high, the output capacitor could be overstressed. Loop Compensation The AOZ1051PI employs peak current mode control for ease of use and fast transient response. Peak current mode control eliminates the double pole effect of the output L&C filter. It also greatly simplifies the compensation loop design. With peak current mode control, the buck power stage can be simplified to be a one-pole and one-zero system in frequency domain. The pole is dominant pole can be calculated by: The zero is a ESR zero due to the output capacitor and its ESR. It is can be calculated by: where; CO is the output filter capacitor, RL is load resistor value, and ESRCO is the equivalent series resistance of output capacitor. The compensation design shapes the converter control loop transfer function for the desired gain and phase. Several different types of compensation networks can be used with the AOZ1051PI. For most cases, a series capacitor and resistor network connected to the COMP pin sets the pole-zero and is adequate for a stable high-bandwidth control loop. In the AOZ1051PI, FB and COMP are the inverting input and the output of the internal error amplifier. A series R and C compensation network connected to COMP provides one pole and one zero. The pole is: where; GEA is the error amplifier transconductance, which is 200 x 10-6 A/V, GVEA is the error amplifier voltage gain, which is 500 V/V, and CC is the compensation capacitor in Figure 1. ΔVO ΔIL ESR CO 8 fC O×× ⎛⎞×= ΔVO ΔIL 8 fC O×× ΔVO ΔIL ESR CO×= ICO_RMS ΔIL fP1 2π CO RL×× fZ1 2π CO ESR CO×× fP2 GEA 2π CC GVEA××
Rev. 1.0 June 2011 www.aosmd.com Page 10 of 14 The zero given by the external compensation network, capacitor CC and resistor RC, is located at: To design the compensation circuit, a target crossover frequency fC to close the loop must be selected. The system crossover frequency is where the control loop has unity gain. The crossover is the also called the converter bandwidth. Generally a higher bandwidth means faster response to load transients. However, the bandwidth should not be too high because of system stability concern. When designing the compensation loop, converter stability under all line and load condition must be considered. Usually, it is recommended to set the bandwidth to be equal or less than 1/10 of the switching frequency. The strategy for choosing R C and CC is to set the cross over frequency with RC and set the compensator zero with CC. Using selected crossover frequency, fC, to calculate RC: where; fC is the desired crossover frequency. For best performance, fC is set to be about 1/10 of the switching frequency; VFB is 0.8V, GEA is the error amplifier transconductance, which is 200 x 10-6 A/V, and GCS is the current sense circuit transconductance, which is
8 A/V
The compensation capacitor CC and resistor RC together make a zero. This zero is put somewhere close to the dominate pole fp1 but lower than 1/5 of the selected crossover frequency. CC can is selected by: The above equation can be simplified to: An easy-to-use application software which helps to design and simulate the compensation loop can be found at www.aosmd.com Thermal Management and Layout Considerations In the AOZ1051PI buck regulator circuit, high pulsing current flows through two circuit loops. The first loop starts from the input capacitors, to the VIN pin, to the LX pad, to the filter inductor, to the output capacitor and load, and then returns to the input capacitor through ground. Current flows in the first loop when the high side switch is on. The second loop starts from the inductor, to the output capacitors and load, to the low side NMOSFET. Current flows in the second loop when the low side NMOSFET is on. In PCB layout, minimizing the area of the two loops will reduce the noise of the circuit and improves efficiency. A ground plane is strongly recommended to connect the input capacitor, the output capacitor, and the PGND pin of the AOZ1051PI. In the AOZ1051PI buck regulator circuit, the major power dissipating components are the AOZ1051PI and the output inductor. The total power dissipation of converter circuit can be measured by input power minus output power: The power dissipation of the inductor can be approximately calculated by the output current and DCR value of the inductor: The actual junction temperature can be calculated by the power dissipation in the AOZ1051PI and the thermal impedance from junction to ambient: The maximum junction temperature of the AOZ1051PI is 150 ºC, which limits the maximum load current capability. The thermal performance of the AOZ1051PI is strongly affected by the PCB layout. Care should be taken during the design process to ensure that the IC will operate under the recommended environmental conditions. fZ2 2π CC RC×× RC fC VO VFB GEA GCS× CC 1.5 2π RC fP1×× CC CO RL× RC Ptotal_loss VIN IIN VO IO×–×= Pinductor_loss IO 2 Rinductor 1.1××= Tjunction Ptotal_loss Pinductor_loss–() Θ × JA=
Rev. 1.0 June 2011 www.aosmd.com Page 11 of 14 Layout Considerations The AOZ1051PI is an exposed pad SO-8 package. Several layout tips are listed for the best electric and thermal performance. 1. The exposed pad (LX) is connected to the internal PFET and NFET drains. Connected a large copper plane to the LX pin to help thermal dissipation. 2. Do not use a thermal relief connection to the VIN pin or the PGND pin. Pour a maximized copper area to the PGND pin and the VIN pin to help thermal dissipation. 3. The input capacitor should be connected as close as possible to the VIN pin and the PGND pin. 4. A ground plane is preferred. If a ground plane is not used, separate PGND from AGND and only connect them at one point to avoid the PGND pin noise coupling to the AGND pin. 5. Make the current trace from the LX pad to L to Co to the PGND as short as possible. 6. Pour copper plane on all unused board area and connect it to stable DC nodes, like VIN, GND or VOUT. 7. Keep sensitive signal trace away from the LX pad.
Rev. 1.0 June 2011 www.aosmd.com Page 12 of 14 Notes: 1. Package body sizes exclude mold flash and gate burrs. 2. Dimension L is measured in gauge plane. 3. Tolerance 0.10mm unless otherwise specified. 4. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact. 5. Die pad exposure size is according to lead frame design. 6. Followed from JEDEC MS-012 Symbols A B C D E e L y θ L1–L1' | Dimensions in millimeters RECOMMENDED LAND PATTERN Min. 1.40 0.00 1.40 0.31 0.17 4.80 3.20 3.10 5.80 3.80 2.21 0.40 UNIT: mm θ Nom. 1.55 0.05 1.50 0.406 4.96 3.40 3.30 6.00 1.27 3.90 2.41
0.40 REF
0.95 0.04
1.04 REF
Max. 1.70 0.10 1.60 0.51 0.25 5.00 3.60 3.50 6.20 4.00 2.61 1.27 0.10 0.12 Dimensions in inches E1 EE3E2 Note 5 L1' L Gauge plane 0.2500 C D 7 (4x) B 3.70 2.20 2.87 2.71 5.74 1.27 0.80 0.635 e A2 A Symbols A B C D E e L y θ L1–L1' | Min. 0.055 0.000 0.055 0.012 0.007 0.189 0.126 0.122 0.228 0.150 0.087 0.016 Nom. 0.061 0.002 0.059 0.016 0.195 0.134 0.130 0.236 0.050 0.153 0.095
0.016 REF
0.037 0.002
0.041 REF
Max. 0.067 0.004 0.063 0.020 0.010 0.197 0.142 0.138 0.244 0.157 0.103 0.050 0.004 0.005
Rev. 1.0 June 2011 www.aosmd.com Page 13 of 14 Tape and Reel Dimensions, SO-8 EP1 Carrier Tape Reel Tape Size 12mm Reel Size ø330 M ø330.00 ±0.50 Package SO-8 (12mm) 6.40 ±0.10 5.20 ±0.10 2.10 ±0.10 1.60 ±0.10 1.50 ±0.10 E 12.00 ±0.10 1.75 ±0.10 5.50 ±0.10 8.00 ±0.10 4.00 ±0.10 2.00 ±0.10 T 0.25 ±0.10 N ø97.00 ±0.10 UNIT: mm G M S K H N W V R Trailer Tape 300mm min. or 75 empty pockets Components Tape Orientation in Pocket Leader Tape 500mm min. or 125 empty pockets Feeding DirectionP0 E T W 13.00 ±0.30 17.40 ±1.00 H ø13.00 +0.50/-0.20 K 10.60 S 2.00 ±0.50 G R V Leader/Trailer and Orientation UNIT: mm
Rev. 1.0 June 2011 www.aosmd.com Page 14 of 14 Part Marking Z1051PI FAY Part Number Code Assembly Lot Code Year & Week Code WLT Fab & Assembly Location As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. This data sheet contains preliminary data; supplementary data may be published at a later date. Alpha & Omega Semiconductor reserves the right to make changes at any time without notice. LIFE SUPPORT POLICY ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.