AO4886 AOSMD | Alldatasheet
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100V Dual N-Channel MOSFET General Description Product Summary VDS I D (at V GS =10V) 3.3A R DS(ON) (at V GS =10V) < 80m Ω R DS(ON) (at V GS = 4.5V) < 91m Ω 100% UIS Tested 100% R g Tested Symbol VDS The AO4886 combines advanced trench MOSFET technology with a low resistance package to provide extremely low R DS(ON) .This device is ideal for boost converters and synchronous rectifiers for consumer, telecom, industrial power supplies and LED backlighting. V Maximum Units Parameter Absolute Maximum Ratings T A=25° C unless otherwise noted 100V Drain-Source Voltage 100 4 5 Top View SOIC-8 Top View Bottom View Pin1 VDS VGS IDM IAS , I AR EAS , E AR TJ, T STG Symbol t ≤ 10s Steady-State Steady-State R θJL Maximum Junction-to-Ambient A TA=25° C 2.00 Maximum Junction-to-Lead Maximum Junction-to-Ambient A D VDrain-Source Voltage 100 Avalanche energy L=0.1mH C Pulsed Drain Current C Continuous Drain Current T A=70° C ° C/W ° C/W 74 62.5 A ID A14 ° C/W W R θJA Units Thermal Characteristics Parameter Typ Max Gate-Source Voltage 2.7 mJ Junction and Storage Temperature Range -55 to 150 ° C 1.28 V±20 TA=25° C TA=70° C Avalanche Current C 3.3 Power Dissipation B PD 4 5 Top View SOIC-8 Top View Bottom View Pin1 Rev 0: Sep 2010 www.aosmd.com Page 1 of 6
VDS =100V, V GS =0V 1 TJ=55° C 5 IGSS ±100 nA VGS(th) Gate Threshold Voltage 1.6 2.2 2.7 V ID(ON) 17 A 63.5 80 TJ=125° C 122 152 70 91 m Ω gFS 20 S VSD 0.74 1 V IS 2.5 A C iss 620 778 942 pF C oss 38 55 81 pF C rss 13 24 35 pF R g 0.7 1.45 2.2 Ω Q g(10V) 13 16.3 20 nC Q g(4.5V) 6.4 8.1 10 nC Q gs 2.2 2.8 3.4 nC Q gd 2.4 4.1 5.8 nC tD(on) 6 ns t 2.5 ns Drain-Source Breakdown Voltage On state drain current I D =250 µA, V GS =0V VGS =10V, V DS =5V VGS =10V, I D =3A Reverse Transfer Capacitance VGS =0V, V DS =50V, f=1MHz SWITCHING PARAMETERS VDS =V GS ID =250 µA VDS =0V, V GS = ±20V Gate-Body leakage current Forward Transconductance Gate Drain Charge Total Gate Charge Electrical Characteristics (T J=25° C unless otherwise noted) STATIC PARAMETERS Parameter Conditions IDSS µAZero Gate Voltage Drain Current R DS(ON) Static Drain-Source On-Resistance m Ω IS=1A,V GS =0V VDS =5V, I D =3A VGS =4.5V, I D =3A Diode Forward Voltage Maximum Body-Diode Continuous Current Input Capacitance Output Capacitance Turn-On DelayTime DYNAMIC PARAMETERS Turn-On Rise Time V =10V, V =50V, R =16.7 Ω , Gate resistance VGS =0V, V DS =0V, f=1MHz Total Gate Charge VGS =10V, V DS =50V, I D =3A Gate Source Charge tr 2.5 ns tD(off) 21 ns tf 2.4 ns trr 14 21 28 ns Q rr 65 94 123 nC THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR TH E CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE N OT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY AR ISING OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN, FUNCTIONS AND RELIABILITY WITHOUT NOTICE. Body Diode Reverse Recovery Time IF=3A, dI/dt=500A/ µs Body Diode Reverse Recovery Charge IF=3A, dI/dt=500A/ µs Turn-On Rise Time Turn-Off DelayTime VGS =10V, V DS =50V, R L=16.7 Ω , R GEN =3 Ω Turn-Off Fall Time A. The value of R θJA is measured with the device mounted on 1in 2 FR-4 board with 2oz. Copper, in a still air environment with T A =25 °C. The value in any given application depends on the user's specific board design. B. The power dissipation P D is based on T J(MAX) =150 °C, using ≤ 10s junction-to-ambient thermal resistance. C. Repetitive rating, pulse width limited by junction temperature T J(MAX) =150 °C. Ratings are based on low frequency and duty cycles to keep initialT J=25 °C. D. The R θJA is the sum of the thermal impedence from junction to lead R θJL and lead to ambient. E. The static characteristics in Figures 1 to 6 are obtained using <300 µs pulses, duty cycle 0.5% max. F. These curves are based on the junction-to-ambient thermal impedence which is measured with the device mounted on 1in 2 FR-4 board with 2oz. Copper, assuming a maximum junction temperature of T J(MAX) =150 °C. The SOA curve provides a single pulse rating. Rev 0: Sep 2010 www.aosmd.com Page 2 of 6
Gate Charge Test Circuit & Waveform VDC DUT Vdd Vgs Vds Vgs RL Rg Vgs Vds 10% 90% Resistive Switching Test Circuit & Waveforms t t rd(on) ton td(off) tf toff Id L Vgs Vds BV Unclamped Inductive Switching (UIS) Test Circuit & Waveforms Vds DSS E = 1/2 LI AR AR VDC Ig Vds DUT VDC Vgs Vgs 10V Qg Qgs Qgd Charge Gate Charge Test Circuit & Waveform VDC DUT Vdd Vgs Vds Vgs RL Rg Vgs Vds 10% 90% Resistive Switching Test Circuit & Waveforms t t rd(on) ton td(off) tf toff Vdd Vgs Id Vgs Rg DUT VDC L Vgs Vds Id Vgs BV I Unclamped Inductive Switching (UIS) Test Circuit & Waveforms Ig Vgs VDC DUT L Vds Vgs Vds Isd Isd Diode Recovery Test Circuit & Waveforms Vds - Vds + IF AR DSS E = 1/2 LI dI/dt IRM rr Vdd Vdd Q = - Idt AR AR trr Rev 0: Sep 2010 www.aosmd.com Page 6 of 6