VP5225 SUTEX | Alldatasheet

Document overview

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Technical content

Features

Low threshold (-2.4V max.) High input impedance Low input capacitance Fast switching speeds Low on-resistance Free from secondary breakdown Low input and output leakage

Applications

Medical Ultrasound imaging Non-destructive evaluation Solid state relays Telecom switches Logic level interfaces – ideal for TTL and CMOS General Description This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. P-Channel Enhancement-Mode Vertical DMOS FET Absolute Maximum Ratings Parameter Value Drain-to-source voltage BVDSS Drain-to-gate voltage BVDGS Gate-to-source voltage ±20V Operating and storage temperature -55OC to +150OC Soldering temperature* 300OC Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. * Distance of 1.6mm from case for 10 seconds.

Ordering Information

Package Option BVDSS/BVDGS (V) RDS(ON) (max) (Ω) ID(ON) (min) (A)3-Lead TO-252 (D-PAK) VP5225 VP5225K4 -250 3.0 -2.5 Pin Configuration 3-Lead TO-252 (D-PAK) (K4) GATE SOURCE DRAIN YY = Year Sealed WW = Week Sealed L = Lot Number YYWW VP5225 LLLLLLL Product Marking 3-Lead TO-252 (D-PAK) (K4) Obsolete

Electrical Characteristics (TA = 25OC unless otherwise specified) Sym Parameter Min Typ Max Units Conditions BVDSS Drain-to-source breakdown voltage -250 - - V VGS = 0V, ID = -250µA VGS(th) Gate threshold voltage -1.0 - -2.4 V VGS = VDS, ID= -1.0mA ΔVGS(th) Change in VGS(th) with temperature - - 4.5 mV/OC VGS = VDS, ID= -1.0mA IGSS Gate body leakage - - -100 nA VGS = ± 20V, VDS = 0V IDSS Zero gate voltage drain current - - -10 µA VGS = 0V, VDS = Max Rating - - -1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125°C ID(ON) On-state drain current -2.5 - - A VGS = -10V, VDS = -25V RDS(ON) Static drain-to-source on-state resistance - - 5.0 Ω VGS = -4.5V, ID = -250mA ΔRDS(ON) Change in RDS(ON) with temperature - - 1.7 %/OC VGS = -10V, ID = -1.0A GFS Forward transductance 500 - - mmho VDS = -25V, ID = -200mA CISS Input capacitance - - 400 pF VGS = 0V, VDS = -25V, f = 1.0MHz COSS Common source output capacitance - - 150 CRSS Reverse transfer capacitance - - 50 td(ON) Turn-on delay time - - 20 ns VDD = -25V, ID = -500mA, RGEN = 25Ω tr Rise time - - 30 td(OFF) Turn-off delay time - - 60 tf Fall time - - 30 VSD Diode forward voltage drop - - -1.8 V VGS = 0V, ISD = -500mA trr Reverse recovery time - 300 - ns VGS = 0V, ISD = -500mA Notes: 2. All A.C. parameters sample tested. Notes: † ID (continuous) is limited by max rated Tj of 150OC. ‡ Mounted on FR4 board, 25mm x 25mm x 1.57mm Thermal Characteristics Package ID (continuous)† (mA) ID (pulsed) (A) Power Dissipation @TA = 25OC (W) θjc (OC/W) θja (OC/W) IDR (mA) IDRM (A) 3-LeadTO-252 (D-PAK) 645 3.0 2.5‡ 6.25 50‡ 645 3.0 Switching Waveforms and Test Circuit 90% 10% 90% 90% 10%10% PULSE GENERATOR VDD RL Output D.U.T. t(ON) td(ON) t(OFF) td(OFF) tFtr INPUT INPUT OUTPUT VDD RGEN -10V Obsolete

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-VP5225 NR053008 3-Lead TO-252 D-PAK Package Outline (K4) Notes: 1. 4 terminal locations are shown, only 3 are functional. Lead number 2 was removed. 1 2 3 L4 L5 bb2 e L Seating Plane Gauge Plane θ D E Detail B Front ViewSide View Rear View Detail B H A Symbol A A1 b b2 b3 c2 D D1 E E1 e H L L1 L2 L3 L4 L5 θ θ1 Dimension (inches) .090 BSC .370 .055 .108 REF .020 BSC .035 - .045 0O 0O JEDEC Registration TO-252, Variation AA, Issue E, June 2004. Drawings not to scale. Obsolete