TP5322 SUTEX | Alldatasheet
Document overview
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Technical content
Features
! Low threshold, -2.4V max. ! High input impedance ! Low input capacitance, 110pFmax. ! Fast switching speeds ! Low on resistance ! Free from secondary breakdown ! Low input and output leakage ! Complementary N- and P-channel devices Application ! Logic level interfaces-ideal for TTL and CMOS ! Battery operated systems ! Photo voltaic devices ! Analog switches ! General purpose line drivers ! Telecom switches Absolute Maximum Ratings Drain-to-Source Voltage BVDSS Drain-to-Gate Voltage BVDGS Gate-to-Source Voltage ±20V Operating and Storage Temperature -55°C to +150°C Soldering Temperature** 300°C **Distance of 1.6mm from case for 10 seconds. General Description These low threshold enhancement-mode (normally-off) transistors utilize an advanced vertical DMOS structure and Supertex's well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally-induced secondary breakdown. Supertex's vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Package Options
Ordering Information
TO-243AA TO-236AB* BVDSS / BVDGS RDS(ON) (max) VGS(th) (max) ID(ON) (min) TP5322N8 TP5322K1 -220V 12Ω -2.4V -0.7A TP5322N8-G* TP5322K1-G* -220V 12Ω -2.4V -0.7A Same as SOT-89. Product supplied on 2000 piece carrier tape reels. *Same as SOT-23. Products supplied on 3000 piece carrier tape reels. TP5322 A042005 * "Green" Certified Package D S D G D S G TO-236AB (SOT-23)* TO-243AA (SOT-89)* Product Marking for SOT-89 TP3C✶ Where ✶=2-week alpha date code Product Marking for SOT-23 P3C✶ Where ✶=2-week alpha date code
Rev. 3 September 14, 2004 Thermal Characteristics Package ID (continuous) ID (pulsed) Power Dissipation @ TA = 25°C θJC °C/W θJA °C/W IDR* IDRM TO-243AA -0.26A -0.90A 1.6W 78** -0.26A -0.9A TO-236AB -0.12A -0.70A 0.36W 200 350 -0.12A -0.7A *ID(continous) is limited by max rated Tj. **Mounted on FR4 board, 25mm x 25mm x 1.57mm. Significant PD increase possible on ceramic substate. Electrical Characteristics (@25°C unless otherwise specified) Symbol Parameter Min Typ Max Units Conditions BVDSS Drain-to-Source Breakdown Voltage -220 V VGS = 0V, ID = -2mA VGS(th) Gate Threshold Voltage -1.0 -2.4 V VGS = VDS, ID = -1mA ∆VGS(th) Change in VGS(th) with Temperature 4.5 mV/°C VGS = VDS, ID = -1mA IGSS Gate Body Leakage -100 nA VGS = ±20V, VDS = 0V -10 µA VGS = 0V, VDS = Max Rating IDSS Zero Gate Voltage Drain Current -1.0 mA VGS = 0V, VDS = 0.8 Max Rating, TA = 125°C ID(ON) On-State Drain Current -0.7 -0.95 A VGS = -10V, VDS = -25V VGS = -4.5V, ID = -100mA RDS(ON) Static Drain-to-Source ON-State Resistance 8.0 Ω VGS = -10V, ID = -200mA ∆RDS(ON) Change in RDS(ON) with Temperature 1.7 %/°C VGS = -10V, ID = -200mA GFS Forward Transconductance 100 250 mmho VDS = -25V, ID = -200mA CISS Input Capacitance 110 COSS Common Source Output Capacitance CRSS Reverse Transfer Capacitance pF VGS = 0V, VDS = -25V f = 1MHz td(ON) Turn-ON Delay Time tr Rise Time td(OFF) Turn-Off Delay Time tf Fall Time ns VDD = -25V, ID = -0.7A RGEN = 25 Ω VSD Diode Forward Voltage Drop -1.8 V VGS = 0V, ISD = -0.5A trr Reverse Recovery Time 300 ns VGS = 0V, ISD = -0.5A Notes: 1) All DC parameters 100% tested at 25°C unless otherwise stated. (Pulsed test: 300µs pulse at 2% duty cycle.) 2) All AC parameters sample tested. Switching Waveforms and Test Circuit RGEN Input Pulse Generator VDD RL D.U.T OUTPUT -10V VDD td(OFF) Input Output tr tf td(ON) t(ON) t(OFF) Doc.# DSFP-TP5322 A042005