TC1550

TC1550_08 SUTEX | Alldatasheet

Document overview

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Technical content

Features

Independent N- and P-channels Electrically isolated N- and P-channels Low input capacitance Fast switching speeds Free from secondary breakdowns Low input and output leakage

Applications

Amplifiers Buffers Piezoelectric transducer drivers General purpose line drivers General Description The Supertex TC1550 consists of a high voltage N-channel and P-channel MOSFET in an 8-Lead SOIC package. This is an enhancement-mode (normally-off) transistor utilizing an advanced vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. N- and P-Channel Enhancement-Mode Dual MOSFET -G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Parameter Value Drain-to-source voltage BVDSS Drain-to-gate voltage BVDGS Gate-to-source voltage ±20V Operating and storage temperature -55°C to + 150°C Soldering temperature* 300°C Device Package Option BVDSS/BVDGS RDS(ON) (Max) 8-Lead SOIC 4.90x3.90mm body 1.75mm height (max) 1.27mm pitch N-Channel (V) P-Channel (V) N-Channel (Ω) P-Channel (Ω) TC1550 TC1550TG-G 500 -500 60 125 Pin Configuration

Ordering Information

YY = Year Sealed WW = Week Sealed L = Lot Number = “Green” Packaging YYWW C1550 L L L L 8-Lead SOIC (TG) (top view) Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. * Distance of 1.6mm from case for 10 seconds. 8-Lead SOIC (TG)

• 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Sym Parameter Min Typ Max Units Conditions BVDSS Drain-to-source breakdown voltage 500 - - V VGS = 0V, ID = 1.0mA VGS(th) Gate threshold voltage 2.0 - 4.0 V VGS = VDS, ID =1.0mA ΔVGS(th) Change in VGS(th) with temperature - -3.8 -5.0 mV/OC VGS = VDS, ID = 1.0mA IGSS Gate body leakage current - - 100 nA VGS = ±20V, VDS = 0V IDSS Zero gate voltage drain current - - 10 µA VGS = 0V, VDS = Max Rating - - 1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125°C ID(ON) On-state drain current - 100 - mA VGS = 5.0V, VDS = 25V 150 350 - VGS = 10V, VDS = 25V RDS(ON) Static drain-to-source on-state resistance - 45 - Ω VGS = 5.0V, ID = 50mA - 40 60 VGS = 10V, ID = 50mA ΔRDS(ON) Change in RDS(ON) with temperature - 1.0 1.7 %/OC VGS = 10V, ID = 50mA GFS Forward transconductance 50 100 - mmho VDS = 25V, ID =50mA CISS Input capacitance - 45 55 pF VGS = 0V, VDS = 25V, f = 1.0MHz COSS Common source output capacitance - 8.0 10 CRSS Reverse transfer capacitance - 2.0 5.0 td(ON) Turn-on delay time - - 10 ns VDD = 25V, ID = 150mA, RGEN = 25Ω tr Rise time - - 15 td(OFF) Turn-off delay time - - 10 tf Fall time - - 10 VSD Diode forward voltage drop - 0.8 - V VGS = 0V, ISD = 500mA trr Reverse recovery time - 300 - ns VGS = 0V, ISD = 500mA N-Channel Switching Waveforms and Test Circuit RGEN Input Pulse Generator VDD RL D.U.T. OUTPUT 10V VDD td(OFF) Input Output tr tftd(ON) t(ON) t(OFF) 10% 90% 90% 10% 90% 10% N-Channel Electrical Characteristics (TA = 25°C unless otherwise specified) Notes: All DC parameters 100% tested at 25°C unless otherwise stated. (Pulsed test: 300µs pulse at 2% duty cycle.) All AC parameters sample tested.

• 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com P-Channel Switching Waveforms and Test Circuit RGEN Input Pulse Generator VDD RL D.U.T. OUTPUT -10V VDD td(OFF) Input Output tr tftd(ON) t(ON t(OFF) 90% 10% 90% 10% 10% 90% Sym Parameter Min Typ Max Units Conditions BVDSS Drain-to-source breakdown voltage -500 - - V VGS = 0V, ID = -1.0mA VGS(th) Gate threshold voltage -2.0 - -4.5 V VGS = VDS, ID = -1.0mA ΔVGS(th) Change in VGS(th) with temperature - 3.5 6.0 mV/OC VGS = VDS, ID = -1.0mA IGSS Gate body leakage current - - 100 nA VGS = ±20V, VDS = 0V IDSS Zero gate voltage drain current - - -10 µA VGS = 0V, VDS = Max Rating - - -1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125°C ID(ON) On-state drain current - -90 - mA VGS = -5.0V, VDS = -25V -100 -240 - VGS = -10V, VDS = -25V RDS(ON) Static drain-to-source on-state resistance - 85 - Ω VGS = -5.0V, ID = -5.0mA - 80 125 VGS = -10V, ID = -10mA ΔRDS(ON) Change in RDS(ON) with temperature - 0.85 - %/OC VGS = -10V, ID = -10mA GFS Forward transconductance 25 40 - mmho VDS = -25V, ID = -10mA CISS Input capacitance - 40 70 pF VGS = 0V, VDS = -25V, f = 1.0MHz COSS Common source output capacitance - 10 20 CRSS Reverse transfer capacitance - 3.0 10 td(ON) Turn-on delay time - 5.0 10 ns VDD = -25V, ID = -100mA, RGEN = 25Ω tr Rise time - 8.0 10 td(OFF) Turn-off delay time - 8.0 15 tf Fall time - 5.0 16 VSD Diode forward voltage drop - -0.8 -1.5 V VGS = 0V, ISD = -100mA trr Reverse recovery time - 200 - ns VGS = 0V, ISD = -100mA P-Channel Electrical Characteristics (TA = 25°C unless otherwise specified) Notes: All DC parameters 100% tested at 25°C unless otherwise stated. (Pulsed test: 300µs pulse at 2% duty cycle.) All AC parameters sample tested.

• 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Typical Application Circuit VDD2 VHVDD1 Supertex MD1213K6 VLVSS2VSS1GND OUTA OUTB INA INB OE 0.47µF +12V 3.3V CMOS Logic Inputs Supertex TC1550TG +250V -250V Piezoelectric Transducer 10nF 250V 10nF 250V 15V 15V Block Diagram SN GN SP GP DP DP DN DN N-Channel P-Channel

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications ©2008 All rights reserved. Unauthorized use or reproduction is prohibited .

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888 www.supertex.com TC1550 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-TC1550 A091608 8-Lead SOIC (Narrow Body) Package Outline (TG) 4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch Seating Plane Gauge Plane L E D e b A A2 Seating Plane A A Top View Side View View B View B θ Note 1 (Index Area D/2 x E1/2) View A-A h h Note 1 Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1 Dimension (mm) 1.27 BSC 0.25 0.40 1.04 REF 0.25 BSC 0O 5O JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005. * This dimension is not specified in the original JEDEC drawing. The value listed is for reference only. Drawings are not to scale. Supertex Doc. #: DSPD-8SOLGTG, Version G090808. Note: This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated. The Pin 1 Identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator.