TC6320_07 SUTEX | Alldatasheet
Document overview
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Technical content
Features
Freedom from secondary breakdown Low input and output leakage Independent, electrically isolated N- and P- channels
Applications
Medical ultrasound transmitters High voltage pulsers Amplifi ers Buffers Piezoelectric transducer drivers General purpose line drivers N- and P- Channel Enhancement-Mode Dual MOSFET General Description The Supertex TC6320 consists of high voltage low threshold N-channel and P-channel MOSFETs in an SO- 8 package. Both MOSFETs have integrated gate-source resistors and gate-source zener diode clamps which are desired for high voltage pulser applications. The TC6320 is a complimentary, high-speed, high voltage, gate-clamped N- and P-channel MOSFET pair in an SO-8 package. These low threshold enhancement-mode (normally-off) transistors utilize an advanced vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coeffi cient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired.
Ordering Information
8-Lead SOIC (Narrow Body) TC6320 TC6320TG TC6320TG-G -G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Parameter Value Drain to source voltage BV DSS Drain to gate voltage BV DGS Operating and storage temperature -55°C to +150°C Soldering temperature 1 +300°C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Note 1. Distance of 1.6mm from case for 10 seconds. Pin Confi guration BVDSS/BVDGS RDS(ON) (MAX) N-Channel P-Channel N-Channel P-Channel 200V -200V 7.0Ω 8.0Ω (top view) N-Channel P-Channel45
N- Channel Electrical Characteristics (TJ = 25°C unless otherwise specifi ed) Symbol Parameter Min Typ Max Units Conditions BVDSS Drain-to-source breakdown voltage 200 - - V V GS = 0V, ID = 2.0mA VGS(th) Gate threshold voltage 1.0 - 2.0 V V GS = VDS, ID = 1.0mA ΔVGS(th) Change in VGS(th) with temperature - - -4.5 mV/ OCV GS = VDS, ID = 1.0mA RGS Gate-Source Shunt Resistor 10 - 50 KΩ I GS = 100µA ΔRGS Change in RGS with Temperature - - TBD %/ OCI GS = 100µA VZGS Gate-Source Zener Voltage 13.2 - 25 V I GS = 2.0mA ΔVZGS Change in VZGS with Temperature - TBD mV/ OCI GS = 2.0mA IDSS Zero gate voltage drain current - - 10.0 µA V DS = Max rating, VGS = 0V - - 1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125OC ID(ON) ON-state drain current 1.0 - - A VGS = 4.5V, VDS = 25V 2.0 - - V GS = 10V, VDS = 25V RDS(ON) Static drain-to-source ON-state resis- tance - - 8.0 Ω VGS = 4.5V, ID = 150mA - - 7.0 V GS = 10V, ID = 1.0A ΔRDS(ON) Change in RDS(ON) with temperature - - 1.0 %/ OCV GS = 4.5V, ID =150mA GFS Forward transconductance 400 - - mmho V DS = 25V, ID = 200mA CISS Input capacitance - - 110 pF VGS = 0V, VDS = 25V, f = 1MHz COSS Common source output capacitance - - 60 CRSS Reverse transfer capacitance - - 23 td(ON) Turn-ON delay time - - 10 ns VDD =25V, ID = 1.0A, RGEN = 25Ω tr Rise time - - 15 td(OFF) Turn-OFF delay time - - 20 tf Fall time - - 15 VSD Diode forward voltage drop - - 1.8 V V GS = 0V, ISD = 0.5A trr Reverse recovery time - 300 - ns V GS = 0V, ISD = 0.5A Notes: 2.All A.C. parameters sample tested. N- Channel Switching Waveforms and Test Circuit Pulse Generator VDD RL D.U.T OUTPUT 10V VDD td(OFF) Input Output tr tftd(ON) t(ON) t(OFF) 10% 90% 90% 10% 90% 10% RGEN Input
P- Channel Electrical Characteristics (TJ = 25°C unless otherwise specifi ed) Symbol Parameter Min Typ Max Units Conditions BVDSS Drain-to-source breakdown voltage -200 - - V V GS = 0V, ID = -2.0µA VGS(th) Gate threshold voltage -1.0 - -2.4 V V GS = VDS, ID = -1.0mA ΔVGS(th) Change in VGS(th) with temperature - - 4.5 mV/ OCV GS = VDS, ID = -1.0mA RGS Gate-source shunt resistor 10 - 50 KΩ I GS = 100µA ΔRGS Change in RGS with temperature - - TBD %/ OCI GS = 100µA VZGS Gate-source zener voltage 13.2 - 25 V I GS = -2mA ΔVZGS Change in RGS with temperature - - TBD mV/ OCI GS = -2mA IDSS Zero gate voltage drain current - - -10 µA V DS = Max rating, VGS = 0V - - -1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125OC ID(ON) ON-state drain current -1.0 - - A VGS = -4.5V, VDS = -25V -2.0 - - V GS = -10V, VDS = -25V RDS(ON) Static drain-to-source ON-state resis- tance -- 1 0 Ω VGS = -4.5V, ID = -150mA ΔRDS(ON) Change in RDS(ON) with temperature - - 1.0 %/ OCV GS = -10V, ID =-200mA GFS Forward transconductance 400 - - mmho V DS = -25V, ID = -200mA CISS Input capacitance - - 200 pF VGS = 0V, VDS = -25V, f = 1MHz COSS Common source output capacitance - - 55 CRSS Reverse transfer capacitance - - 30 td(ON) Turn-ON delay time - - 10 ns VDD = -25V, ID = -1.0A, RGEN = 25Ω tr Rise time - - 15 td(OFF) Turn-OFF delay time - - 20 tf Fall time - - 15 VSD Diode forward voltage drop - - -1.8 V V GS = 0V, ISD = -0.5A trr Reverse recovery time - 300 - ns V GS = 0V, ISD = -0.5A Notes: 2.All A.C. parameters sample tested. P- Channel Switching Waveforms and Test Circuit RGEN Input Pulse Generator VDD RL D.U.T OUTPUT -10V VDD td(OFF) Input Output tr tftd(ON) t(ON) t(OFF) 90% 10% 90% 10% 10% 90%
Doc.# DSFP-TC6320 C112106 TC6320 (The package drawing(s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) 8-Lead SO (TG) Package Outline 45° 5° - 15° (4 PLCS) 4.90 ± 0.10 1.27BSC 6.00 ± 0.20 3.90 ± 0.10 Notes: 1. All dimensions in millimeters. Angles in degrees. 2. If the corner is not chamfered, then a Pin 1 identifier must be located within the area indicated. Note 2
1.75 MAX
1.25 MIN
0.25 - 0.50 0° - 8° 0.40 - 1.27 0.17 - 0.25 Top View Side View End View Note 2