VN0606L-G SUTEX | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 3

Technical content

Features

Free from secondary breakdown Low power drive requirement Ease of paralleling Low CISS and fast switching speeds Excellent thermal stability Integral source-drain diode High input impedance and high gain

Applications

Amplifiers Switches Power supply circuits Drivers (relays, hammers, solenoids, lamps, memories, displays, bipolar transistors, etc.) General Description This enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon- gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. N-Channel Enhancement-Mode Vertical DMOS FET Absolute Maximum Ratings Parameter Value Drain-to-source voltage BVDSS Drain-to-gate voltage BVDGS Gate-to-source voltage ±30V Operating and storage temperature -55OC to +150OC Soldering temperature* 300OC Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. * Distance of 1.6mm from case for 10 seconds.

Ordering Information

Package Options BVDSS/BVDGS (V) RDS(ON) (max) (Ω) ID(ON) (min) (A)TO-92 VN0606 VN0606L-G 60 3.0 1.5 -G indicates package is RoHS compliant (‘Green’) Pin Configurations TO-92 (L) GATE SOURCE DRAIN YY = Year Sealed WW = Week Sealed = “Green” Packaging Si VN 0 6 0 6 L YYWW TO-92 (L) Product Marking Package may or may not include the following marks: Si or

  • 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Electrical Characteristics (TA = 25OC unless otherwise specified) Sym Parameter Min Typ Max Units Conditions Notes: † ID (continuous) is limited by max rated Tj . Thermal Characteristics Switching Waveforms and Test Circuit 90% 10% 90% 90% 10%10% PULSE GENERATOR VDD RL OUTPUT D.U.T. t(ON) td(ON) t(OFF) td(OFF)tr INPUT INPUT OUTPUT 10V VDD RGEN tf BVDSS Drain-to-source breakdown voltage 60 - - V VGS = 0V, ID = 10µA VGS(th) Gate threshold voltage 0.8 - 2.0 V VGS = VDS, ID = 1.0mA IGSS Gate body leakage - - 100 nA VGS = ±30V, VDS = 0V IDSS Zero gate voltage drain current - - 10 µA VGS = 0V, VDS = 50V - - 500 VGS = 0V, VDS = 50V, TA = 125°C ID(ON) On-state drain current 1.5 - - A VGS = 10V, VDS = 10V RDS(ON) Static drain-to-source on-state resistance - - 3.0 Ω VGS = 10V, ID = 1.0A GFS Forward transductance 170 - - mmho VDS = 10V, ID = 500mA CISS Input capacitance - - 50 pF VGS = 0V, VDS = 25V, f = 1.0MHz COSS Common source output capacitance - - 25 CRSS Reverse transfer capacitance - - 5.0 t(ON) Turn-on delay time - - 10 ns VDD = 25V, ID = 600mA, RGEN = 25Ωt(OFF) Turn-off delay time - - 10 VSD Diode forward voltage drop - 0.85 - V VGS = 0V, ISD = 470mA Notes: All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) All A.C. parameters sample tested. Package ID (continuous)† (mA) ID (pulsed) (A) Power Dissipation @TC = 25OC (W) θjc (OC/W) θja (OC/W) IDR (mA) IDRM (A) TO-92 330 1.6 1.0 125 170 330 1.6

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications ©2009 All rights reserved. Unauthorized use or reproduction is prohibited .

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888 www.supertex.com VN0606 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-VN0606 A042709 3-Lead TO-92 Package Outline (L) Symbol A b c D E E1 e e1 L Dimensions (inches) JEDEC Registration TO-92. * This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc.#: DSPD-3TO92N3, Version E041009. Seating Plane Front View Side View Bottom View E D L e c 1 2 3 b A