VN0300_13 SUTEX | Alldatasheet
Document overview
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Technical content
Features
► Free from secondary breakdown ► Low power drive requirement ► Ease of paralleling ► Low CISS and fast switching speeds ► Excellent thermal stability ► Integral source-drain diode ► High input impedance and high gain
Applications
► Motor controls ► Converters ► Amplifiers ► Switches ► Power supply circuits ► Drivers (relays, hammers, solenoids, lamps, memories, displays, bipolar transistors, etc.) General Description This enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. N-Channel Enhancement-Mode Vertical DMOS FET Absolute Maximum Ratings Parameter Value Drain-to-source voltage BVDSS Drain-to-gate voltage BVDGS Gate-to-source voltage ±30V Operating and storage temperature -55OC to +150OC Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. TO-92 Product Marking Package may or may not include the following marks: Si or Pin Configuration TO-92 GATE SOURCE DRAIN Product Summary BVDSS/BVDGS RDS(ON) (max) IDSS (min) 30V 1.2Ω 1.0A Typical Thermal Resistance Package θja TO-92 132OC/W
Ordering Information
Part Number Package Option Packing VN0300L-G TO-92 1000/Bag VN0300L-G P002 TO-92 2000/Reel VN0300L-G P003 VN0300L-G P005 VN0300L-G P013 VN0300L-G P014 -G denotes a lead (Pb)-free / RoHS compliant package. Contact factory for Wafer / Die availablity. Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.
Supertex inc. www.supertex.com Doc.# DSFP-VN0300 B081913 VN0300 Electrical Characteristics (TA = 25OC unless otherwise specified) Sym Parameter Min Typ Max Units Conditions Switching Waveforms and Test Circuit 90% 10% 90% 90% 10%10% Pulse Generator VDD RL OUTPUT D.U.T. t(ON) td(ON) t(OFF) td(OFF)tr INPUT INPUT OUTPUT 10V VDD RGEN tf BVDSS Drain-to-source breakdown voltage 30 - - V VGS = 0V, ID = 10µA VGS(th) Gate threshold voltage 0.8 - 2.5 V VGS = VDS, ID= 1.0mA IGSS Gate body leakage - - 100 nA VGS = ± 30V, VDS = 0V IDSS Zero gate voltage drain current - - 10 µA VGS = 0V, VDS = Max Rating - - 500 VGS = 0V, VDS = 30V, TA = 125°C ID(ON) On-state drain current 1.0 - - A VGS = 10V, VDS = 10V RDS(ON) Static drain-to-source on-state resistance - - 3.3 Ω VGS = 5.0V, ID = 300mA - - 1.2 VGS = 10V, ID = 1.0A GFS Forward transductance 200 - - mmho VDS = 10V, ID = 500mA CISS Input capacitance - - 190 pF VGS = 0V, VDS = 20V, f = 1.0MHz COSS Common source output capacitance - - 110 CRSS Reverse transfer capacitance - - 50 t(ON) Turn-on time - - 30 ns VDD = 25V, ID = 1.0A, RGEN = 25Ωt(OFF) Turn-off time - - 30 VSD Diode forward voltage drop - 0.9 - V VGS = 0V, ISD = 630mA Notes: 2. All A.C. parameters sample tested. Notes: † ID (continuous) is limited by max rated Tj . Thermal Characteristics Package ID (continuous)† ID (pulsed) Power Dissipation @TC = 25OC IDR † IDRM TO-92 640mA 3.0A 1.0W 640mA 3.0A
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888 www.supertex.com VN0300 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-VN0300 B081913 3-Lead TO-92 Package Outline (L) Symbol A b c D E E1 e e1 L Dimensions (inches) JEDEC Registration TO-92. * This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc.#: DSPD-3TO92N3, Version E041009. Seating Plane Front View Side View Bottom View E D L e c 1 2 3 b A