TP2635_07 SUTEX | Alldatasheet

Document overview

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Technical content

Features

Low threshold — -2.0V max. High input impedance Low input capacitance Fast switching speeds Low on resistance Free from secondary breakdown Low input and output leakage Complementary N- and P-channel devices

Applications

Logic level interfaces – ideal for TTL and CMOS Solid state relays Battery operated systems Photo voltaic drives Analog switches General purpose line drivers Telecom switches General Description These low threshold enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coeffi cient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired.

Ordering Information

BVDSS/BVDGS RDS(ON) (max) V GS(th) (max) I D(ON) (min) SO-8 TO-92 TP2635 - TP2635N3 -350V 15Ω -2.0V -0.7A - TP2635N3-G TP2640 TP2640LG TP2640N3 -400V 15Ω -2.0V -0.7A TP2640LG-G TP2640N3-G -G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Parameter Value Drain to source voltage BV DSS Drain to gate voltage BV DGS Gate to source voltage ±20V Operating and storage temperature -55°C to +150°C Soldering temperature 1 +300°C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Note 1. Distance of 1.6mm from case for 10 seconds. Pin Confi gurations S G D TO-92 SO-8 (top view) NC NC S G D D D D P- Channel Enhancement-Mode Vertical DMOS FETs

Electrical Characteristics (TJ = 25°C unless otherwise specifi ed) Symbol Parameter Min Typ Max Units Conditions BVDSS Drain-to-source break- down voltage TP2640 -400 -- V V GS = 0V, ID = -2.0mATP2635 -350 VGS(th) Gate threshold voltage -0.8 - -2.0 V V GS = VDS, ID = -1.0mA ΔVGS(th) Change in VGS(th) with temperature - - 5 mV/ OCV GS = VDS, ID = -1.0mA IGSS Gate body leakage - -100 nA V GS = ±20V, VDS = 0V IDSS Zero gate voltage drain current - - -1.0 µA V DS = -100V, VGS = 0V -10.0 µA V DS = Max rating, VGS = 0V -1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125OC ID(ON) ON-state drain current 0.7 - - A V GS = -10V, VDS = -25V RDS(ON) Static drain-to-source ON-state resistance - 12 15 Ω VGS = -2.5V, ID = -200mA 11 15 V GS = -4.5V, ID = -150mA 11 15 V GS = -10V, ID = -300mA ΔRDS(ON) Change in RDS(ON) with temperature - - 0.75 %/ OCV GS = -10V, ID = -300mA GFS Forward transconductance 200 - - m V DS = -25V, ID = -300mA CISS Input capacitance - - 300 pF V GS = 0V, VDS = -25V, f = 1MHzCOSS Common source output capacitance - - 50 CRSS Reverse transfer capacitance - - 12 td(ON) Turn-ON delay time - - 10 ns VDD = 25V, ID = 2.0A, RGEN = 25Ω tr Rise time - - 15 td(OFF) Turn-OFF delay time - - 60 tf Fall time - - 40 VSD Diode forward voltage drop - - -1.8 V V GS = 0V, ISD = 200mA trr Reverse recovery time - 300 - ns V GS = 0V, ISD = 1.0A Notes: 2.All A.C. parameters sample tested. N- Channel Switching Waveforms and Test Circuit Thermal Characteristics Package I D (continuous)1 ID (pulsed) Power Dissipation @TC = 25OC Θjc (OC/W) Θjc (OC/W) I DR

1 IDRM

SO-8 -210mA -1.25A 1.3W 2 24 96 2 210mA -1.25A TO-92 -180mA -0.8A 1.0W 125 170 -180mA -0.8A Notes: 1. ID (continuous) is limited by max rated Tj. 2. Mounted on FR4 board, 25mm x 25mm x 1.57mm Ω 90% 10% 90%90% 10% 10% PULSE GENERATOR VDD RL OUTPUT D.U.T. t(ON) td(ON) t(OFF) td(OFF) tFtr INPUT INPUT OUTPUT VDD Rgen -10V

Typical Performance Curves Output Characteristics -2.0 -1.6 -1.2 -0.8 -0.4 VDS (volts) I )serepma(D Saturation Characteristics VDS (volts) I )serepma(D Maximum Rated Safe Operating Area -1 -1000 -100-10 -10 -1.0 -0.1 -0.01 -0.001 VDS (volts) I )serepma(D Thermal Response Characteristics )dezilamron( ecnatsiseR lamrehT 1.0 0.8 0.6 0.4 0.2 0.001 10 0.01 0.1 1.0 tp (seconds) T ransconductance vs. Drain Current 1.0 0.8 0.6 0.4 0.2 0 -0.8 -0.4 G SF )snemeis( ID (amperes) Power Dissipation vs. Temperature 01 5 0 10050 2.0 1.6 1.2 0.8 0.4 1257525 TC C)°( DP )sttaw( TO-92 TC = 25 °C PD = 1.0W SO-8 TO-92 TA = -55°C VDS = -25V 25°C 125°C -1.2 -2.0 -1.6 -1.0 -0.8 -0.6 -0.4 -0.2 VGS = -10V -3V -4V -6V -8VVGS = -10V -8V -6V -3V -4V SO-8 (pulsed) TC = 25°C TO-92 (DC) TO-92 (pulsed) SO-8 (DC)

Typical Performance Curves (cont.) Gate Drive Dynamic Characteristics Q (nanocoulombs)G V SG )stlov( Tj )ht(SGV) dezilamron( )NO(SDR) dezilamron( VTH and RDS Variation with Temperature C)°( On-Resistance vs. Drain Current (amperes)D )smho()NO(SDR Variation with TemperatureDSS SSD )dezilamron(VB C)°(Tj Transfer Characteristics VGS (volts) I )serepma(D Capacitance vs. Drain-to-Source Voltage 400 )sdarafocip( C VDS (volts) I BV 0 -10 -20 -30 -40 200 300 100 0 - 2- 4- 6- 8 - 1 0 -2.0 -1.6 -1.2 -0.8 -0.4 -50 0 50 100 150 1.1 1.0 1.2 1.0 0.8 0.6 0.4 -10 012 3 45 -50 0 50 100 150 263pF VDS = -10V VDS = -40V 678pF VGS = -4.5V VGS = -10V VGS = -2.5V +125°C f = 1MHz CISS COSS CRSS 0.9 2.5 2.0 1.5 1.0 0.5 RDS(ON)@ -10V, -0.3A 25°CTA = -55°C VDS = -25V V(th) @ -1mA

(The package drawing(s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) 8-Lead SOIC Package Outline (LG) 45° 5° - 15° (4 PLCS) 4.90 ± 0.10 1.27BSC 6.00 ± 0.20 3.90 ± 0.10 Notes: 1. All dimensions in millimeters. Angles in degrees. 2. If the corner is not chamfered, then a Pin 1 identifier must be located within the area indicated. Note 2

1.75 MAX

1.25 MIN

0.25 - 0.50 0° - 8° 0.40 - 1.27 0.17 - 0.25 Top View Side View End View Note 2 3-Lead TO-92 Package Outline (N3) 1 2 3 Seating Plane 2 3 Front View 0.175 - 0.205 0.170 - 0.210

0.500 MIN

0.014 - 0.022 0.045 - 0.055 0.095 - 0.105 0.125 - 0.165

0.135 MIN

0.080 - 0.105 0.014 - 0.022 Side View Bottom View Notes: All dimensions are in millimeters; all angles in degrees. Doc.# DSFP-TP2635_TP2640 C032807