TP2520

TP2520_07 SUTEX | Alldatasheet

Document overview

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Technical content

Features

Low threshold — -2.4V max. High input impedance Low input capacitance — 125pF max. Fast switching speeds Low ON-resistance Free from secondary breakdown Low input and output leakage Complementary N and P-channel devices

Applications

Logic level interfaces – ideal for TTL and CMOS Solid state relays Battery operated systems Photo voltaic drives Analog switches General purpose line drivers Telecom switches General Description This low threshold enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coeffi cient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally- induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. P-Channel Enhancement Mode Vertical DMOS FETs -G indicates package is RoHS compliant (‘Green’) Parameter Value Drain-to-source voltage BV DSS Drain-to-gate voltage BV DGS Gate-to-source voltage ±20V Operating and storage temperature -55°C to +150°C Soldering temperature* 300°C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. * Distance of 1.6 mm from case for 10 seconds. Absolute Maximum Ratings

Ordering Information

(V) RDS(ON) max (Ω) VGS(th) max (V) ID(ON) min (A) Package Option TO-243AA (SOT-89) -200 12 -2.4 -0.75 TN2520N8-G Pin Confi guration Product Marking TO-243AA (SOT-89) (N8) TO-243AA (SOT-89) (N8) W = Code for week sealedTP5CW GATE SOURCE DRAIN DRAIN

(continuous)* (mA) ID (pulsed) (A) Power Dissipation @ TA = 25OC (W) θjc OC/W θja OC/W IDR* (mA) IDRM (A) * ID (continuous) is limited by max rated Tj . † Mounted on FR5 board, 25mm x 25mm x 1.57mm. Switching Waveforms and Test Circuit 90% 10% 90% 90% 10%10% PULSE GENERATOR VDD RL Output D.U.T. t(ON) td(ON) t(OFF) td(OFF) tFtr INPUT INPUT OUTPUT VDD RGEN -10V Symbol Parameter Min Typ Max Units Conditions Electrical Characteristics (TA = 25°C unless otherwise specifi ed) BVDSS Drain-to-source breakdown voltage -200 - - V V GS = 0V, ID = -2.0mA VGS(th) Gate threshold voltage -1.0 - -2.4 V V GS = VDS, ID= -1.0mA ∆VGS(th) Change in VGS(th) with temperature - - 4.5 mV/ OCV GS = VDS, ID= -1.0mA IGSS Gate body leakage - - -100 nA V GS = ± 20V, VDS = 0V IDSS Zero gate voltage drain current - -- 1 0 μ A V GS = 0V, VDS = Max Rating - -1.0 mA VGS = 0V, VDS = 0.8 Max Rating, TA = 125°C ID(ON) ON-state drain current -0.25 -0.7 - A VGS = -4.5V, VDS = -25V RDS(ON) Static drain-to-source ON-State resistance - 10 15 Ω VGS = -4.5V, ID = -100mA 8.0 12 V GS = -10V, ID = -200mA ∆RDS(ON) Change in RDS(ON) with temperature - - 1.7 %/ OCV GS = -10V, ID = -200mA GFS Forward transconductance 100 250 - mmho V DS = -25V, ID = -200mA CISS Input capacitance - 75 125 pF VGS = 0V, VDS = -25V, f = 1.0 MHz COSS Common source output capacitance - 20 85 CRSS Reverse transfer capacitance - 10 35 td(ON) Turn-ON delay time - - 10 ns VDD = -25V, ID = -0.75A, RGEN = 25Ω tr Rise time - - 15 td(OFF) Turn-OFF delay time - - 20 tf Fall time - - 15 VSD Diode forward voltage drop - - -1.8 V V GS = 0V, ISD = -0.5A trr Reverse recovery time - 300 - ns V GS = 0V, ISD = -0.5A Notes: (1) All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) (2) All A.C. parameters sample tested.

Typical Performance Curves Output Characteristics -2.5 -2.0 -1.5 -1.0 -0.5 Saturation Characteristics -2.0 -1.6 -1.2 -0.8 -0.4 Maximum Rated Safe Operating Area -1 -1000 -100-10 -0.1 -1.0 -10 -0.01 Thermal Response Characteristics )dezilamron( ecnatsiseR lamrehT 1.0 0.8 0.6 0.4 0.2 0.001 10 0.01 0.1 1 Transconductance vs. Drain Current 1.0 0.8 0.6 0.4 0.2 0 -2.0 -0.4 Power Dissipation vs. Ambient Temperature 01 5 0 10050 2.0 1257525 0 -10 -20 -30 -50 -40 VGS = -10V -4V -3V 0- 2- 4 - 6 - 1 0 -8 -6V -6V -8V -4V -8V TA = 25°C TA = 125°C TA = -55°C -0.8 -1.2 -1.6 TO-243AA (DC) 1.0 -3V TO-243AA VDS VDS(volts) ID )serepma( ID )serepma( VGS = -10V VDS = -25V G SF )snemeis( PD )sttaw( VDS tP (seconds) ID )sserepma( TO-243AA (pulsed) TA (°C)ID (amperes) TA = 25°C TO-243AA TA = 25 °C PD = 1.6W

Typical Performance Curves (cont.) Gate Drive Dynamic Characteristics QG (nanocoulombs) V )ht(SG )dezilamron( V(th) and RDS Variation with Temperature On-Resistance vs. Drain Current R )NO(SD )smho( BVDSS Variation with Temperature VB SSD )dezilamron( Transfer Characteristics Capacitance vs. Drain-to-Source Voltage 200 )sdarafocip( C 0 -10 -20 -30 -40 150 100 0 -2 -4 -6 -8 -10 -2.5 -2.0 -1.5 -1.0 -0.5 -50 0 50 100 150 1.1 1.0 1.2 1.1 1.0 0.9 0.8 -10 -50 0 50 100 150 73pF f = 1MHz 0.9 200pF 2.5 2.0 1.5 1.0 0.5 V(th) @ -1mA RDS(ON) @ -10V, -0.2A Tj (°C) I D (amperes) VGS = -10V VGS = -4.5V R )NO(SD )dezilamron( Tj (°C)VGS (volts) VDS = -25V TA = -55°C 25°C 125°C ID )serepma( VDS = -10V VDS = -40V VDS (volts) V SG )stlov( CISS COSSCRSS

Doc.# DSFP - TP2520 A101507 3-Lead TO-243AA (SOT-89) Package Outline (N8) Symbol A b b1 C D D1 E E1 e e1 H L Dimensions (mm) 1.50 BSC 3.00 BSC 3.94 0.89 JEDEC Registration TO-243, Variation AA, Issue C, July 1986. Drawings not to scale.