TP2424 SUTEX | Alldatasheet
Document overview
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Technical content
Features
❏ Low threshold ❏ High input impedance ❏ Low input capacitance ❏ Fast switching speeds ❏ Free from secondary breakdown ❏ Low input and output leakage ❏ Complementary N- and P-channel devices
Applications
❏ Logic level interfaces – ideal for TTL and CMOS ❏ Solid state relays ❏ Linear Amplifiers ❏ Power Management ❏ Analog switches ❏ Telecom switches Low Threshold DMOS Technology These low threshold enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well- proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. P-Channel Enhancement-Mode Vertical DMOS FETs Absolute Maximum Ratings Drain-to-Source Voltage BV DSS Drain-to-Gate Voltage BV DGS Gate-to-Source Voltage ± 20V Operating and Storage Temperature -55 °C to +150°C Soldering Temperature* 300 °C * Distance of 1.6 mm from case for 10 seconds. Low Threshold
Ordering Information
Order Number / PackageBVDSS /R DS(ON) VGS(th) ID(ON) BVDGS (max) (max) (min) TO-243AA* Die -240V 8.0 Ω -2.4V -800mA TP2424N8 TP2424ND * Same as SOT-89. Product supplied on 2000 piece carrier tape reels. Package Option Note: See Package Outline section for dimensions. TO-243AA (SOT-89) G D S D Product marking for TO-243AA: TP4C❋ where ❋ = 2-week alpha date code
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com 11/12/01 ©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. TP2424 Switching Waveforms and Test Circuit 90% 10% 90%90% 10% 10% PULSE GENERATOR VDD RL OUTPUT D.U.T. t(ON) td(ON) t(OFF) td(OFF) tFtr INPUT INPUT OUTPUT VDD Rgen -10V Thermal Characteristics Package I D (continuous)* I D (pulsed) Power Dissipation θjc θja IDR*I DRM @ TA = 25°C °C/W °C/W TO-243AA -316mA -1.9A 1.6W † 15 78 † -316mA -1.9A * ID (continuous) is limited by max rated T j. † Mounted on FR5 board, 25mm x 25mm x 1.57mm. Significant P D increase possible on ceramic substrate. Symbol Parameter Min Typ Max Unit Conditions BVDSS Drain-to-Source -240 V V GS = 0V, ID = -250µABreakdown Voltage VGS(th) Gate Threshold Voltage -1.0 -2.4 V V GS = VDS, ID= -1.0mA ∆VGS(th) Change in VGS(th) with Temperature 4.5 mV/ °CV GS = VDS, ID= -1.0mA IGSS Gate Body Leakage -100 nA V GS = ± 20V, VDS = 0V IDSS Zero Gate Voltage Drain Current -10.0 µAV GS = 0V, VDS = Max Rating -1.0 mA V GS = 0V, VDS = 0.8 Max Rating TA = 125°C ID(ON) ON-State Drain Current -0.3 V GS = -4.5V, VDS = -25V -0.8 V GS = -10V, VDS = -25V RDS(ON) 10.0 Ω VGS = -4.5V, ID = -150mA
8.0 V GS = -10V, ID = -500mA
∆RDS(ON) Change in RDS(ON) with Temperature 0.75 %/ °CV GS = -10V, ID = -500mA GFS Forward Transconductance 150 m V DS = -25V, ID = -200mA CISS Input Capacitance 200 COSS Common Source Output Capacitance 100 pF CRSS Reverse Transfer Capacitance 40 td(ON) Turn-ON Delay Time 20 tr Rise Time 30 td(OFF) Turn-OFF Delay Time 35 tf Fall Time 25 VSD Diode Forward Voltage Drop -1.5 V V GS = 0V, ISD = -500mA trr Reverse Recovery Time 300 ns V GS = 0V, ISD = -500mA Notes: 2.All A.C. parameters sample tested. Electrical Characteristics (@ 25°C unless otherwise specified) A ns VDD = -25V, ID = -250mA, RGEN = 25Ω VGS = 0V, VDS = -25V f = 1.0 MHz Static Drain-to-Source ON-State Resistance Ω