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Technical content

Features

► Low threshold (-2.4V max.) ► High input impedance ► Low input capacitance (95pF typical) ► Fast switching speeds ► Low on-resistance ► Free from secondary breakdown ► Low input and output leakage

Applications

► Logic level interfaces - ideal for TTL and CMOS ► Solid state relays ► Battery operated systems ► Photo voltaic drives ► Analog switches ► General purpose line drivers ► Telecom switches General Description This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. P-Channel Enhancement-Mode Vertical DMOS FET Absolute Maximum Ratings Parameter Value Drain-to-source voltage BVDSS Drain-to-gate voltage BVDGS Gate-to-source voltage ±20V Operating and storage temperature -55OC to +150OC Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Pin Configuration TO-92 (N3) GATE SOURCE DRAIN YY = Year Sealed WW = Week Sealed = “Green” Packaging SiTP 0604 YYWW TO-92 (N3) Product Marking Package may or may not include the following marks: Si or

Ordering Information

Part Number Package Option Packing TP0604N3-G 3-Lead TO-92 1000/Bag TP0604N3-G P002 3-Lead TO-92 2000/Reel TP0604N3-G P003 TP0604N3-G P005 TP0604N3-G P013 TP0604N3-G P014 TP2404NW Die in wafer form --- TP2404NJ Die on adhesive tape --- TP2404ND Die in waffle pack --- Product Summary BVDSS/BVDGS (V) RDS(ON) (max) (Ω) ID(ON) (min) (A) VGS(th) (max) (V) -40 2.0 -2.0 -2.4 For packaged products, -G indicates package is RoHS compliant (‘Green’). TO-92 taping specifications and winding styles per EIA-468 Standard. Devices in Wafer / Die form are RoHS compliant (‘Green’). Refer to Die Specification VF57 for layout and dimensions.

Supertex inc. www.supertex.com Doc.# DSFP-TP0604 C082012 Electrical Characteristics (TA = 25OC unless otherwise specified) Sym Parameter Min Typ Max Units Conditions BVDSS Drain-to-source breakdown voltage -40 - - V VGS = 0V, ID = -2.0mA VGS(th) Gate threshold voltage -1.0 - -2.4 V VGS = VDS, ID= -1.0mA ΔVGS(th) Change in VGS(th) with temperature - -3.0 -4.5 mV/OC VGS = VDS, ID= -1.0mA IGSS Gate body leakage - - -100 nA VGS = ± 20V, VDS = 0V IDSS Zero gate voltage drain current - - -10 µA VGS = 0V, VDS = Max Rating - - -1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125°C ID(ON) ON-state drain current -0.4 -0.6 - A VGS = -5.0V, VDS = -20V RDS(ON) Static drain-to-source on-state resistance - 2.0 3.5 Ω VGS = -5.0V, ID = -250mA ΔRDS(ON) Change in RDS(ON) with temperature - - 1.2 %/OC VGS = -10V, ID = -1.0A GFS Forward transductance 400 600 - mmho VDS = -20V, ID = -1.0A CISS Input capacitance - 95 150 pF VGS = 0V, VDS = -20V, f = 1.0MHz COSS Common source output capacitance - 85 120 CRSS Reverse transfer capacitance - 35 60 td(ON) Turn-on delay time - 5.0 8.0 ns VDD = -20V, ID = -1.0A, RGEN = 25Ω tr Rise time - 7.0 18 td(OFF) Turn-off delay time - 10 15 tf Fall time - 6.0 19 VSD Diode forward voltage drop - -1.3 -2.0 V VGS = 0V, ISD = -1.5A trr Reverse recovery time - 300 - ns VGS = 0V, ISD = -1.5A Notes: 2. All A.C. parameters sample tested. Notes: † ID (continuous) is limited by max rated Tj . Thermal Characteristics Package ID (continuous)† (A) ID (pulsed) (A) Power Dissipation @TA = 25OC (W) θja (OC/W) IDR (A) IDRM (A) Switching Waveforms and Test Circuit 90% 10% 90% 90% 10%10% Pulse Generator VDD RL OUTPUT D.U.T. t(ON) td(ON) t(OFF) td(OFF) tftr INPUT RGEN INPUT OUTPUT VDD -10V

Supertex inc. www.supertex.com Doc.# DSFP-TP0604 C082012 Typical Performance Curves Saturation Characteristics Power Dissipation vs. Case Temperature 0 15010050 2.0 1.0 1257525 -6V -8V -4V TO-92 ID (amperes) TC (OC) PD (watts) VDS (volts) VGS = -10V Thermal Response Characteristics Thermal Resistance (normalized) 1.0 0.8 0.6 0.4 0.2 0.001 0.01 0.1 1.0 10 tp (seconds) TO-92 PD = 1.0W TC = 25OC Output Characteristics 0 -10 -20 -30 -40 VDS (volts) ID (amperes) Maximum Rated Safe Operating Area -1 -10 -100 -1000 -0.1 -1.0 -10 -0.01 TC = 25OC TO-92 (DC) VDS (volts) ID (amperes) Transconductance vs. Drain Current TA = -55OC GFS (siemens) ID (amperes) VDS = -25V TA = -150OC TA = 25OC 1.0 0.8 0.6 0.4 0.2 0 -1.0 -2.0 -3.0 -5V -7V -9V -6V -8V -4V VGS = -10V -5V -7V -9V

Supertex inc. www.supertex.com Doc.# DSFP-TP0604 C082012 Typical Performance Curves (cont.) Gate Drive Dynamic Characteristics -10 QG (nanocoulombs) 180pF 75pF VGS (volts) VDS = -10V 1.4 1.2 1.0 0.8 0.6 -50 0 50 100 150 2.0 0.8 1.6 0.4 1.2 V(th) and RDS Variation with Temperature On-Resistance vs. Drain Current 7.5 6.0 5.0 3.0 1.5 RDS(ON) (ohms) VGS = -5.0V 1.1 1.0 0.9 -50 0 50 100 150 BVDSS (normalized) Tj (OC) Transfer Characteristics VGS (volts) ID (amperes) VDS = -25OC TA = -55 O C TA = 150 O C Capacitance vs. Drain-to-Source Voltage 200 150 100 0 -10 -20 -30 -40 C (picofarads) f = 1.0MHz CISS COSS CRSS VDS (volts) ID (amperes) BVDSS Variation with Temperature TA = 25 O C V(th) @ -1.0mA RDS(ON) @ -10V, -1.0A Tj (OC) VGS = -10V VGS(th) (normalized) RDS(ON) (normalized) VDS = -40V

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2012 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888 www.supertex.com TP0604 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-TP0604 C082012 3-Lead TO-92 Package Outline (N3) Symbol A b c D E E1 e e1 L Dimensions (inches) JEDEC Registration TO-92. * This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc.#: DSPD-3TO92N3, Version E041009. Seating Plane Front View Side View Bottom View E D L e c 1 2 3 b A