TP0620_13 SUTEX | Alldatasheet

Document overview

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Technical content

Features

► Low threshold (-2.4V max.) ► High input impedance ► Low input capacitance (85pF typical) ► Fast switching speeds ► Low on-resistance ► Free from secondary breakdown ► Low input and output leakage

Applications

► Logic level interfaces - ideal for TTL and CMOS ► Solid state relays ► Battery operated systems ► Photo voltaic drives ► Analog switches ► General purpose line drivers ► Telecom switches General Description This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. P-Channel Enhancement-Mode Vertical DMOS FET Absolute Maximum Ratings Parameter Value Drain-to-source voltage BVDSS Drain-to-gate voltage BVDGS Gate-to-source voltage ±20V Operating and storage temperature -55OC to +150OC Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Pin Configuration TO-92 GATE SOURCE DRAIN TO-92 Product Marking Package may or may not include the following marks: Si or

Ordering Information

Part Number Package Option Packing TP0620N3-G 3-Lead TO-92 1000/Bag TP0620N3-G P002 3-Lead TO-92 2000/Reel TP0620N3-G P003 TP0620N3-G P005 TP0620N3-G P013 TP0620N3-G P014 Product Summary BVDSS/BVDGS RDS(ON) (max) ID(ON) (min) VGS(th) (max) -200V 12Ω -0.75A -2.4V -G denotes a lead (Pb)-free / RoHS compliant package. Contact factory for Wafer / Die availablity. Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant. Typical Thermal Resistance Package θja TO-92 132OC/W

Supertex inc. www.supertex.com Doc.# DSFP-TP0620 C081313 TP0620 Electrical Characteristics (TA = 25OC unless otherwise specified) Sym Parameter Min Typ Max Units Conditions BVDSS Drain-to-source breakdown voltage -200 - - V VGS = 0V, ID = -2.0mA VGS(th) Gate threshold voltage -1.0 - -2.4 V VGS = VDS, ID= -1.0mA ΔVGS(th) Change in VGS(th) with temperature - - -4.5 mV/OC VGS = VDS, ID= -1.0mA IGSS Gate body leakage - - -100 nA VGS = ± 20V, VDS = 0V IDSS Zero gate voltage drain current - - -10 µA VGS = 0V, VDS = Max Rating - - -1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125°C ID(ON) ON-state drain current -0.25 - - A VGS = -5.0V, VDS = -25V -0.75 - - VGS = -10V, VDS = -25V RDS(ON) Static drain-to-source on-state resistance - 9.0 15 Ω VGS = -5.0V, ID = -100mA - 7.0 12 VGS = -10V, ID = -200mA ΔRDS(ON) Change in RDS(ON) with temperature - - 1.7 %/OC VGS = -10V, ID = -200mA GFS Forward transductance 100 150 - mmho VDS = -25V, ID = -400mA CISS Input capacitance - 85 150 pF VGS = 0V, VDS = -25V, f = 1.0MHz COSS Common source output capacitance - 30 85 CRSS Reverse transfer capacitance - 10 35 td(ON) Turn-on delay time - - 10 ns VDD = -25V, ID = -750mA, RGEN = 25Ω tr Rise time - - 15 td(OFF) Turn-off delay time - - 20 tf Fall time - - 16 VSD Diode forward voltage drop - - -1.8 V VGS = 0V, ISD = -500mA trr Reverse recovery time - 300 - ns VGS = 0V, ISD = -500mA Notes: 2. All A.C. parameters sample tested. Notes: † ID (continuous) is limited by max rated Tj . Thermal Characteristics Switching Waveforms and Test Circuit 90% 10% 90% 90% 10%10% Pulse Generator VDD RL OUTPUT D.U.T. t(ON) td(ON) t(OFF) td(OFF) tftr INPUT RGEN INPUT OUTPUT VDD -10V Package ID (continuous)† ID (pulsed) Power Dissipation @TA = 25OC IDR † IDRM TO-92 -175mA -800mA 1.0W -175mA -800mA

Supertex inc. www.supertex.com Doc.# DSFP-TP0620 C081313 TP0620 Typical Performance Curves BVDSS Variation with Temperature BVDSS (normalized) 1.15 1.10 1.05 1.00 0.95 0.90 -50 0 50 100 150 Tj (OC) On-Resistance vs. Drain Current RDS(ON) (ohms) ID (amperes) VGS = -5.0V VGS = -10V Transfer Characteristics -2.0 -1.0 0 -2 -4 -6 -8 -10 VGS (volts) ID (amperes) VDS = -25V TA = -55OC TA = 25OC TA = 125OC 1.2 1.1 1.0 0.9 0.8 0.7 V(th) and RDS Variation with Temperature VGS(th) (normalized) 1.66 1.33 1.00 0.66 0.33 RDS(ON) (normalized) RDS(ON) @ -10V, -0.2A V(th) @ -1.0mA -50 0 50 100 150 Tj (OC) Capacitance vs. Drain-to-Source Voltage VDS (volts) 0 -10 -20 -30 -40 C (picofarads) 200 150 100 f = 1MHz CISS COSS CRSS VDS = -10V VDS = -40V 170pf 45pf Gate Drive Dynamic Characteristics QG (nanocoulombs) -10 VGS (volts)

Supertex inc. www.supertex.com Doc.# DSFP-TP0620 C081313 TP0620 Typical Performance Curves (cont.) VDS (volts) Output Characteristics ID (amperes) 0 -10 -20 -30 -40 -50 -2.0 -1.6 -1.2 -0.8 -0.4 VDS (volts) VGS = -10V -8V -4V -6V Saturation Characteristics -1.0 -0.8 -0.6 -0.4 -0.2 0 -2 -4 -6 -8 -10 ID (amperes) VDS (volts) VGS = -10V -8V -4V -6V Transconductance vs. Drain Current ID (amperes) GFS (millisiemens) 250 200 150 100 TA = 125OC TA = 25OC TA = -55OC VDS = -25V 0 25 50 75 100 125 150 Power Dissipation vs. Case Temperature 2.0 1.0 TO-92 PD (watts) TC (OC) Maximum Rated Safe Operating Area ID (amperes) -10 -1.0 -0.1 -0.01 TO-92 (DC) TC = 25OC Thermal Response Characteristics 0.001 0.01 0.1 1.0 10 1.0 0.8 0.6 0.4 0.2 TO-92 PD = 1W TC = 25OC tP (seconds) Thermal Resistance (normalized)

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888 www.supertex.com TP0620 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-TP0620 C081313 3-Lead TO-92 Package Outline (N3) Symbol A b c D E E1 e e1 L Dimensions (inches) JEDEC Registration TO-92. * This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc.#: DSPD-3TO92N3, Version E041009. Seating Plane Front View Side View Bottom View E D L e c 1 2 3 b A