TN2540_07 SUTEX | Alldatasheet

Document overview

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Technical content

Features

Low threshold — 2.0V max High input impedance Low input capacitance — 125pF max Fast switching speeds Low ON-resistance Free from secondary breakdown Low input and output leakage Complementary N and P-channel devices

Applications

Logic level interfaces — ideal for TTL and CMOS Solid state relays Battery operated systems Photo voltaic devices Analog switches General purpose line drivers Telecom switches General Description The Supertex TN2540 is a low threshold enhancement- mode transistor that utilizes an advanced vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors, and the high input impedance and positive temperature coeffi cient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Low Threshold N-Channel Enhancement-Mode Vertical DMOS FET Switching Waveforms and Test Circuit 90% 10% 90% 90% 10%10% PULSE GENERATOR VDD RL OUTPUT D.U.T. t(ON) td(ON) t(OFF) td(OFF) tFtr INPUT INPUT OUTPUT 10V VDD RGEN

Ordering Information

(V) RDS(ON) (max) (Ω) VGS(th) (max) (V) ID(ON) (min) (A)TO-92 TO-243AA (SOT-89) Die* TN2540 TN2540N3-G TN2540N8-G TN2540ND 400 12 2.0 1.0 -G indicates package is RoHS compliant (‘Green’) * MIL visual screening available. Absolute Maximum Ratings Parameter Value Drain to source voltage BV DSS Drain to gate voltage BV DGS Gate to source voltage ±20V Operating and storage temperature -55°C to +150°C Soldering temperature* 300°C * Distance of 1.6mm from case for 10 seconds. Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Pin Confi guration Product Marking TO-92 (N3) YY = Year Sealed WW = Week Sealed = “Green” Packaging TN 2540 YYWW W = Code for week sealedTN5DW TO-243AA (SOT-89) (N8) TO-243AA (SOT-89) (top view) S G D TO-92 (front view) GATE SINKDRAIN DRAIN Thermal Characteristics Package ID (continuous) (mA) ID (pulsed) (A) Power Dissipation @TA = 25OC (W) θjc (OC/W) θja (OC/W) IDR (mA) IDRM (A) TO-92 175 2.0 1.0 125 170 175 2.0 TO-243AA (SOT-89) 260 1.8 1.6 ‡ 15 78‡ 260 1.8 Notes: † ID (continuous) is limited by max rated TJ . ‡ Mounted on FR5 board, 25mm x 25mm x 1.57mm.

Electrical Characteristics (@ 25°C unless otherwise specifi ed) Symbol Parameter Min Typ Max Units Conditions BVDSS Drain-to-source breakdown voltage 400 - - V V GS = 0V, ID = 100µA VGS(th) Gate threshold voltage 0.6 - 2.0 V V GS = VDS, ID = 1.0mA ΔVGS(th) VGS(th) change with temperature - -2.5 -4.0 mV/ OCV GS = VDS, ID = 1.0mA IGSS Gate body leakage current - - 100 nA V GS = ±20V, VDS = 0V IDSS Zero gate voltage drain current - - 10 µA V GS = 0V, VDS = Max rating - - 1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125OC ID(ON) ON-state drain current 0.3 0.5 - A VGS = 4.5V, VDS = 25V 0.75 1.0 - V GS = 10V, VDS = 25V RDS(ON) Static drain-to-source ON-state resistance - 8.0 12 Ω VGS = 4.5V, ID = 150mA - 8.0 12 V GS = 10V, ID = 500mA ΔRDS(ON) Change in RDS(ON) with temperature - - 0.75 %/ OCV GS = 10V, ID = 500mA GFS Forward transconductance 125 200 - mmho V DS = 25V, ID = 100mA CISS Input capacitance - 95 125 pF VGS = 0V, VDS = 25V, f = 1.0MHz COSS Common source output capacitance - 20 70 CRSS Reverse transfer capacitance - 10 25 td(ON) Turn-ON delay time - - 20 ns VDD = 25V, ID = 1.0A, RGEN = 25Ω tr Rise time - - 15 td(OFF) Turn-OFF delay time - - 25 tf Fall time - - 20 VSD Diode forward voltage drop - - 1.8 V V GS = 0V, ISD = 200mA trr Reverse recovery time - 300 - ns V GS = 0V, ISD = 1.0A Notes: 2.All A.C. parameters sample tested.

Typical Performance Curves

Typical Performance Curves (cont.) Gate Drive Dynamic Characteristics Q (nanocoulombs)G V SG )stlov( Tj )ht(SGV) dezilamron( )NO(SDR) dezilamron( V DS(th) and R Variation with Temperature C)°( On-Resistance vs. Drain Current (amperes)D )smho()NO(SDR Variation with TemperatureDSS SSD )dezilamron(VB C)°(Tj Transfer Characteristics VGS (volts) I )serepma(D Capacitance vs. Drain-to-Source Voltage 200 )sdarafocip( C VDS (volts) I BV 01 0 2 0 3 0 4 0 100 02468 1 0 1.5 1.2 0.9 0.6 0.3 -50 0 50 100 150 1.1 1.0 0.9 1.4 1.2 1.0 0.8 0.6 2.5 2.0 1.5 1.0 0.5 -50 0 50 100 150 VDS = 40V V 95pF DS = 10V VGS = 4.5V VGS = 10V T = -55A C° VDS = 25V 25°C 125°C f = 1MHz CISS COSSCRSS 260 pF (th)V @ 1mA R @ 10V, 0.5ADS(ON) 150

E D L e C 1 2 3 b A 3-Lead TO-92 Package Outline (N3) Symbol A b C D E E1 e e1 L Dimension (inches) Drawings not to scale.

(The package drawing(s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-TN2540 A082307 3-Lead TO-243AA (SOT-89) Package Outline (N8) Symbol A b b1 C D D1 E E1 e e1 H L Dimensions (mm) 1.50 BSC 3.00 BSC 3.94 0.89 JEDEC Registration TO-243, Variation AA, Issue C, July 1986. Drawings not to scale. D E H e A C L Top View Side View b