TN1504 SUTEX | Alldatasheet
Document overview
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Technical content
Features
Low threshold - 2.0V max. High input impedance Low input capacitance - 50pF typical Fast switching speeds Low on resistance Free from secondary breakdown Low input and output leakage Complementary N- and P-channel devices
Applications
Logic level interfaces – ideal for TTL and CMOS Solid state relays Battery operated systems Photo voltaic drives Analog switches General purpose line drivers Telecom switches General Description These low threshold enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combi- nation produces devices with the power handling capabilities of bipolar transistors, and with the high input impedance and positive temperature coeffi cient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally -induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input im- pedance, low input capacitance, and fast switching speeds are desired. Absolute Maximum Ratings Parameter Value Drain-to-source voltage BV DSS Drain-to-source voltage BV DGS Drain-to-source voltage ±20V Operating and storage temperature -55 OC to +150OC Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.
Ordering Information
RDS(ON) (max) VGS(th) (max) ID(ON) (min)Die* TN1504 TN1504NW 40V 3.0Ω 2.0V 2.0A TN1506 TN1506NW 60V 3.0Ω 2.0V 2.0A TN1510 TN1510NW 100V 3.0Ω 2.0V 2.0A * Die in wafer form.
Doc.# DSFP-TN1504/TN1506/TN1510 062706 TN1504/TN1506/TN1510 Symbol Parameter Min Typ Max Units Conditions Electrical Characteristics (@25OC unless otherwise specifi ed) Switching Waveforms and Test Circuit BVDSS Drain-to-source break- down voltage TN1504 40 -- V V GS= 0V, ID = 1.0mATN1506 60 TN1510 100 VGS(th) Gate threshold voltage 0.6 - 2.0 V VGS = VDS, ID = 0.5mA ∆VGS(th) Change in VGS(th) with temperature - -3.8 -5.0 mV/ OC VGS = VDS, ID = 1.0mA IGSS Gate body leakage - 0.1 100 nA VGS = ±20V, VDS = 0V IDSS Zero gate voltage drain current -- μA VGS =0V, VDS = Max Rating VGS = 0V, VDS = 0.8 Max Rating TA = 125OC500 ID(ON) ON-state drain current - 1.4 - A VGS = 5V, VDS = 25V -3 . 4- VGS = 10V, VDS = 25V RDS(ON) Static drain-to-source ON-state resistance - 2.0 4.5 Ω VGS = 4.5V, ID = 250mA - 1.6 3.0 VGS = 10V, ID = 500mA ∆RDS(ON) Change in RDS(ON) with temperature - 0.6 1.1 %/ OC VGS = 10V, ID = 0.5A GFS Forward transconductance 225 400 - mmho VDS = 25V, ID = 500mA CISS Input capacitance -5 0 6 0 pF V GS = 0V, VDS = 25V f = 1 MHzCOSS Common source output capacitance -2 5 3 5 CRSS Reverse transfer capacitance - 4.0 8.05 td(ON) Turn-ON delay time - 2.0 5.0 ns VDD = 25V, ID = 1.0A RGEN = 25Ω tr Rise time - 3.0 5.0 td(OFF) Turn-OFF delay time - 6.0 7.0 tf Fall time - 3.0 6.0 VSD Diode forward voltage drop - 1.0 1.5 V VGS = 0V, ISD = 0.5A trr Reverse recovery time - 400 - ns VGS = 0V, ISD = 0.5A 90% 10% 90% 90% 10%10% PULSE GENERATOR VDD RL OUTPUT D.U.T. t(ON) td(ON) t(OFF) td(OFF) tFtr INPUT INPUT OUTPUT 10V VDD RGEN Notes: 2. All A.C. parameters sample tested.