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Document overview
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Technical content
Features
► High voltage, vertical DMOS technology ► Integrated gate-to-source resistor ► Integrated gate-to-source Zener diode ► Typical peak output +/-3.5A at 50V ► Low threshold, low on-resistance ► Low input & output capacitance ► Fast switching speeds ► Electrically isolated N- and P-MOSFET pairs
Applications
► High voltage pulsers ► Amplifiers ► Buffers ► Piezoelectric transducer drivers ► General purpose line drivers ► Logic level interfaces Six Pair, N- and P-Channel Enhancement-Mode MOSFET General Description The Supertex TC8020 consists of six pairs of high voltage, low threshold N- and P-channel MOSFETs in a 56-lead QFN package. All MOSFETs have integrated gate-to-source resistors and gate-to-source Zener diode clamps which are desired for high voltage pulser applications. The complimentary, high-speed, high voltage, gate-clamped N- and P-channel MOSFET pairs utilize an advanced vertical DMOS structure and Supertex’s well- proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input and output capacitance, and fast switching speeds are desired. Typical Application 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF TX(B) TX(A) TC8020MD1715 AVDD SELA POSA NEGA POSB NEGB SELB OP1A ON1A OP2A ON2A OP3A ON3A OP1B ON2A OP2B ON2B OP3B ON3B GP1 GN1 GP2 GN2 GP3 GN3 GP4 GN4 GP5 GN5 GP6 GN6 AGND VLL/EN +12V GND AVSS(SUB) VSS 1.8 to 3.3V CMOS Input Logic VDD1 VDD2 -12V +12V +12V +3.3V -12V VPP2 SP2 VPP1 SP1SP3 SP4SP5SP6 SN3 SN2 SN1 VNN1 VNN2 SN5 SN4SN6PAD DP1 DN1 DP2 DN2 DP3 DN3 DP4 DN4 DP5 DN5 DP6 DN6
Supertex inc. www.supertex.com Doc.# DSFP-TC8020 C091112 Absolute Maximum Ratings Parameter Value Drain-to-source voltage BVDSS Drain-to-gate voltage BVDGS Operating and storage temperature -55°C to +150°C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. * Distance of 1.6mm from case for 10 seconds. Pin Configuration 56-Lead QFN (K6) Top View 56-Lead QFN (K6) Package Marking Package may or may not include the following marks: Si or Thermal Characteristics Package θja 56-Lead QFN (K6) 27OC/W Note: 1.0oz, 4-layer, 3”x4” PCB TC8020K6 LLLLLLLLL YYWW AAA CCC L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = “Green” Packaging
Ordering Information
Part Number Package Option Packing TC8020K6-G 56-Lead QFN (8x8) 250/Tray -G indicates package is RoHS compliant (‘Green’) Product Summary BVDSS/BVDGS (V) RDS(ON) (max) (Ω) N-Channel P-Channel N-Channel P-Channel 200 -200 8.0 9.5
Supertex inc. www.supertex.com Doc.# DSFP-TC8020 C091112 N-Channel Electrical Characteristics (TA = 25°C unless otherwise specified) Sym Parameter Min Typ Max Units Conditions BVDSS Drain-to-source breakdown voltage 200 - - V VGS = 0V, ID = 1.0mA VGS(th) Gate threshold voltage 1.0 - 2.4 V VGS = VDS, ID = 1.0mA ΔVGS(th) Change in VGS(th) with temperature - - -4.5 mV/OC VGS = VDS, ID = 1.0mA RGS Gate-to-source shunt resistor 5.0 - 26 KΩ IGS = 100µA VZGS Gate-to-source Zener voltage 13.2 - 25 V IGS = 2.0mA IDSS Zero gate voltage drain current - - 10.0 µA VDS = Max rating, VGS = 0V - - 1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125OC ID(ON) On-state drain current 1.2 1.8 - A VGS = 4.5V, VDS = 25V 2.0 3.2 - VGS = 10V, VDS = 25V RDS(ON) Static drain-to-source on-state resistance - 6.0 9.0 Ω VGS = 4.5V, ID = 150mA - 5.3 8.0 VGS = 10V, ID = 1.0A ΔRDS(ON) Change in RDS(ON) with temperature - - 1.0 %/OC VGS = 10V, ID =1.0A GFS Forward transconductance 400 - - mmho VDS = 25V, ID = 500mA CISS Input capacitance - 50 - pF VGS = 0V, VDS = 25V, f = 1.0MHz COSS Common source output capacitance - 18 - CRSS Reverse transfer capacitance - 7.0 - td(ON) Turn-on delay time - - 10 ns VDD =25V, ID = 500mA, RGEN = 25Ω tr Rise time - - 15 td(OFF) Turn-off delay time - - 20 tf Fall time - - 15 VSD Diode forward voltage drop - - 1.8 V VGS = 0V, ISD = 500mA trr Reverse recovery time - 300 - ns VGS = 0V, ISD = 500mA Notes: 2. All A.C. parameters sample tested. N-Channel Switching Waveforms and Test Circuit 10V VDD Input Output 10% 90% 90% 10% 90% 10% RGEN Input Pulse Generator VDD RL D.U.T OUTPUT tr tftd(ON) t(ON) td(OFF) t(OFF)
Supertex inc. www.supertex.com Doc.# DSFP-TC8020 C091112 P-Channel Electrical Characteristics (TA = 25°C unless otherwise specified) Sym Parameter Min Typ Max Units Conditions BVDSS Drain-to-source breakdown voltage -200 - - V VGS = 0V, ID = -1.0mA VGS(th) Gate threshold voltage -1.0 - -2.4 V VGS = VDS, ID = -1.0mA ΔVGS(th) Change in VGS(th) with temperature - - 4.5 mV/OC VGS = VDS, ID = -1.0mA RGS Gate-to-source shunt resistor 5.0 - 26 KΩ IGS = -100µA VZGS Gate-to-source Zener voltage -13.2 - -24.0 V IGS = -2.0mA IDSS Zero gate voltage drain current - - -10 µA VDS = Max rating, VGS = 0V - - -1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125OC ID(ON) On-state drain current -0.80 -1.25 - A VGS = -4.5V, VDS = -25V RDS(ON) Static drain-to-source on-state resistance 7.0 10 Ω VGS = -4.5V, ID = -150mA ΔRDS(ON) Change in RDS(ON) with temperature - - 1.0 %/OC VGS = -10V, ID =-1.0A GFS Forward transconductance 400 - - mmho VDS = -25V, ID = -500mA CISS Input capacitance - 55 - pF VGS = 0V, VDS = -25V, f = 1.0MHz COSS Common source output capacitance - 20 - CRSS Reverse transfer capacitance - 8.0 - td(ON) Turn-on delay time - - 10 ns VDD = -25V, ID = -1.0A, RGEN = 25Ω tr Rise time - - 15 td(OFF) Turn-off delay time - - 20 tf Fall time - - 15 VSD Diode forward voltage drop - - -1.8 V VGS = 0V, ISD = -500mA trr Reverse recovery time - 300 - ns VGS = 0V, ISD = -500mA Notes: 2. All A.C. parameters sample tested. P-Channel Switching Waveforms and Test Circuit RGEN Input Pulse Generator VDD RL D.U.T Output -10V VDD Input Output tr tftd(ON) t(ON) 90% 10% 90% 10% 10% 90% td(OFF) t(OFF)
Supertex inc. www.supertex.com Doc.# DSFP-TC8020 C091112 Test Circuit VDD2 GN2 VSS VDD1 High Speed Gate Buffers SP1 DP1 100Ω DN1 SP2 SN2 DP2 DN2 DP3 DN3 OP1 GP1 ON1 GN1 Control Logic and Level Translation VLL/EN SEL POS NEG GND OP2 GP2 ON2 OP3 GP3 GN3ON3 SN3 SP3 VPP2 VNN2 VNN1 MD1715
1 OF 2-CH TC8020
-12V VSSAVSS -12V GND +12V +12V AVDD +12V PAD PAD VDD2 VDD1 VDD1 High Speed Gate Buffers SN1
Supertex inc. www.supertex.com Doc.# DSFP-TC8020 C091112 Circuit Pin Layout Pin Description Pin Function Description
1 GN1 Gate of N-MOSFET 1
2 GN2 Gate of N-MOSFET 2
3 NC No Connection
4 GN3 Gate of N-MOSFET 3
5 GP3 Gate of P-MOSFET 3
6 NC No Connection
7 SN3 Source of N-MOSFET 3
8 SN6 Source of N-MOSFET 6
9 NC No Connection
10 GP6 Gate of P-MOSFET 6
11 GN6 Gate of N-MOSFET 6
12 NC No Connection
13 GN5 Gate of N-MOSFET 5
14 GN4 Gate of N-MOSFET 4
15 GP5 Gate of P-MOSFET 5
16 GP4 Gate of P-MOSFET 4
17 NC No Connection
18 SN5 Source of N-MOSFET 5
TX(A) TX(B)
Supertex inc. www.supertex.com Doc.# DSFP-TC8020 C091112 Pin Function Description
19 NC No Connection
20 SN4 Source of N-MOSFET 4
21 NC No Connection
22 VSUB Die attachment substrate, must be grounded externally.
23 NC No Connection
24 SP4 Source of P-MOSFET 4
25 NC No Connection
26 SP5 Source of P-MOSFET 5
27 NC No Connection
28 NC No Connection
29 DP4 Drain of P-MOSFET 4
30 DN4 Drain of N-MOSFET 4
31 DP5 Drain of P-MOSFET 5
32 DN5 Drain of N-MOSFET 5
33 DP6 Drain of P-MOSFET 6
34 DN6 Drain of N-MOSFET 6
35 SP6 Source of P-MOSFET 6
36 SP3 Source of P-MOSFET 3
37 DP3 Drain of P-MOSFET 3
38 DN3 Drain of N-MOSFET 3
39 DP2 Drain of P-MOSFET 2
40 DN2 Drain of N-MOSFET 2
41 DP1 Drain of P-MOSFET 1
42 DN1 Drain of N-MOSFET 1
43 NC No Connection
44 NC No Connection
45 SP2 Source of P-MOSFET 2
46 NC No Connection
47 SP1 Source of P-MOSFET 1
48 NC No Connection
49 VSUB Die attachment substrate, must be grounded externally.
50 NC No Connection
51 SN1 Source of N-MOSFET 1
52 NC No Connection
53 SN2 Source of N-MOSFET 2
54 NC No Connection
55 GP1 Gate of P-MOSFET 1
56 GP2 Gate of P-MOSFET 2
Note: Thermal Pad must be grounded externally. Pin Description (cont.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry an d specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2012 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888 www.supertex.com (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) TC8020 Doc.# DSFP-TC8020 C091112 56-Lead QFN Package Outline (K6) 8.00x8.00mm body, 1.00mm height (max), 0.50mm pitch Symbol A A1 A3 b D D2 E E2 e L L1 θ Dimension (mm) MIN 0.80 0.00 0.20 REF 0.50 BSC 0.30 0.00 0O JEDEC Registration MO-220, Variation VLLD-2, Issue K, June 2006. * This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings are not to scale. Supertex Doc.#: DSPD-56QFNK68X8P050, Version A031010. Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square. Seating Plane Top View Side View Bottom View D E View B View B Note 3 Note 2 Note 1 (Index Area D/2 x E/2) Note 1 (Index Area D/2 x E/2) e b L A θ