TC7920 SUTEX | Alldatasheet
Document overview
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Technical content
Features
► High voltage Vertical DMOS technology ► Integrated drain output high voltage diodes ► Integrated gate-to-source resistor ► Integrated gate-to-source Zener diode ► Low threshold, Low on-resistance ► Low input & output capacitance ► Fast switching speeds ► Electrically isolated N- and P-MOSFET pairs
Applications
► High voltage pulsers ► Amplifiers ► Buffers ► Piezoelectric transducer drivers ► General purpose line drivers ► Logic level interfaces Two Pair, N- and P-Channel Enhancement-Mode MOSFET with Drain-Diodes General Description The Supertex TC7920 consists of two pairs of high voltage, low threshold N-channel and P-channel MOSFETs in a 12-Lead DFN package. All MOSFETs have integrated the output drain high voltage diodes, gate-to-source resistors and gate-to-source Zener diode clamps which are desired for high voltage pulser applications. The complimentary, high-speed, high voltage, gate- clamped N and P-channel MOSFET pairs utilize an advanced vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input and output capacitance, and fast switching speeds are desired. Typical Application Circuit 1.8 to 5.0V Logic Imputs OUTB VDD VH INA INB OE 0.1µF +10V Supertex TC7920 DAMP VLGND INC IND VSS +PULSE -PULSE ENAB VPP +100V 10nF Supertex MD1822 0.47µF OUTA OUTD OUTC 1.0µF 1.0µF VNN -100V
Supertex inc. www.supertex.com Doc.# DSFP-TC7920 B080613 TC7920 Absolute Maximum Ratings Parameter Value Drain-to-source voltage BVDSS Drain-to-gate voltage BVDGS Operating and storage temperature -55°C to +150°C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. 12-Lead DFN Package Marking Package may or may not include the following marks: Si or Note: 1.0oz, 4-layer, 3”x4” PCB. 7920 YWLL Y = Last Digit of Year Sealed W = Code for Week Sealed L = Lot Number = “Green” Packaging Pin Configuration 12-Lead DFN (top view) SN1 DN1 DP1 SP1 DN2 DP2 GN1 GP1 GN2 SN2 GP2 SP2 Thermal Pad Typical Thermal Resistance Package θja 12-Lead DFN 42OC/W
Ordering Information
Part Number Package Option Packing TC7920K6-G 12-Lead DFN 3000/Reel Product Summary BVDSS/BVDGS RDS(ON) (max) N-Channel P-Channel N-Channel P-Channel 200V -200V 7.0Ω 8.0Ω Sym Parameter Min Typ Max Unit Condition VR Breakdown voltage 200 - - V IR = 100µA VF Forward voltage - 1.25 - V IF = 100mA IFM Park forward current - 3.0 - A Pulse width = 1.0μs, D% = 1%, One diode IR Reverse current - 1.0 - µA VR = 100 V, TA = 25OC - 100 - VR = 100 V, TA = 125OC trr Reverse recovery time - 1.0 - µs IF = IR = 10mA, IRR = 1.0 mA, RL = 100Ω Drain Output Diodes Pin Description Pin # Function Description Pin # Function Description
1 GN1 Gate of N-MOSFET 1 7 DP2 Drain of P-MOSFET 2
2 GP1 Gate of P-MOSFET 1 8 DN2 Drain of N-MOSFET 2
3 GN2 Gate of N-MOSFET 2 9 SP1 Source of P-MOSFET 1
4 SN2 Source of N-MOSFET 2 10 DP1 Drain of P-MOSFET 1
5 GP2 Gate of P-MOSFET 2 11 DN1 Drain of N-MOSFET 1
6 SP2 Source of P-MOSFET 2 12 SN1 Source of N-MOSFET 1
Thermal Pad Die attachment substrate, must be grounded externally
Supertex inc. www.supertex.com Doc.# DSFP-TC7920 B080613 TC7920 N-Channel Switching Waveforms and Test Circuit 10% 90% 90% 10% 90% 10% RGEN INPUT Pulse Generator VDD RL D.U.T OUTPUT tr tftd(ON) t(ON) td(OFF) t(OFF) 10V INPUT VDD OUTPUT N-Channel Electrical Characteristics (TA = 25°C unless otherwise specified) Sym Parameter Min Typ Max Units Conditions BVDSS Drain-to-source breakdown voltage 200 - - V VGS = 0V, ID = 2.0mA VGS(th) Gate threshold voltage 1.0 - 2.4 V VGS = VDS, ID = 1.0mA ΔVGS(th) Change in VGS(th) with temperature - - -4.5 mV/OC VGS = VDS, ID = 1.0mA RGS Gate-to-source shunt resistor 10 - 50 KΩ IGS = 100µA VZGS Gate-to-source Zener voltage 13.2 - 25 V IGS = 2.0mA IDSS Zero gate voltage drain current - - 10.0 µA VDS = Max rating, VGS = 0V - - 1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125OC ID(ON) On-state drain current 0.9 - - A VGS = 5.0V, VDS = 25V 2.0 - - VGS = 10V, VDS = 50V RDS(ON) Static drain-to-source on-state resistance - - 13 Ω VGS = 5.0V, ID = 150mA - - 10 VGS = 10V, ID = 1.0A ΔRDS(ON) Change in RDS(ON) with temperature - - 1.0 %/OC VGS = 5.0V, ID =150mA GFS Forward transconductance 300 - - mmho VDS = 25V, ID = 500mA CISS Input capacitance - 52 - pF VGS = 0V, VDS = 25V, f = 1.0MHz COSS Common source output capacitance - 6.9 - CRSS Reverse transfer capacitance - 1.3 - td(ON) Turn-on delay time - - 10 ns VDD =25V, ID = 1.0A, RGEN = 25Ω tr Rise time - - 15 td(OFF) Turn-off delay time - - 20 tf Fall time - - 15 VSD Diode forward voltage drop - - 1.8 V VGS = 0V, ISD = 500mA trr Reverse recovery time - 300 - ns VGS = 0V, ISD = 500mA Notes: 2. All A.C. parameters sample tested.
Supertex inc. www.supertex.com Doc.# DSFP-TC7920 B080613 TC7920 P-Channel Electrical Characteristics (TA = 25°C unless otherwise specified) Sym Parameter Min Typ Max Units Conditions BVDSS Drain-to-source breakdown voltage -200 - - V VGS = 0V, ID = -2.0mA VGS(th) Gate threshold voltage -1.0 - -2.4 V VGS = VDS, ID = -1.0mA ΔVGS(th) Change in VGS(th) with temperature - - 4.5 mV/OC VGS = VDS, ID = -1.0mA RGS Gate-to-source shunt resistor 10 - 50 KΩ IGS = 100µA VZGS Gate-to-source Zener voltage 13.2 - 25 V IGS = -2.0mA IDSS Zero gate voltage drain current - - -10 µA VDS = Max rating, VGS = 0V - - -1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125OC ID(ON) On-state drain current -0.7 - - A VGS = -5.0V, VDS = -25V -2.0 - - VGS = -10V, VDS = -50V RDS(ON) Static drain-to-source on-state resistance - - 15 Ω VGS = -5.0V, ID = -150mA ΔRDS(ON) Change in RDS(ON) with temperature - - 1.0 %/OC VGS = -10V, ID =-200mA GFS Forward transconductance 300 - - mmho VDS = -25V, ID = -500mA CISS Input capacitance - 54 - pF VGS = 0V, VDS = -25V, f = 1.0MHz COSS Common source output capacitance - 7.5 - CRSS Reverse transfer capacitance - 2.6 - td(ON) Turn-on delay time - - 10 ns VDD = -25V, ID = -1.0A, RGEN = 25Ω tr Rise time - - 15 td(OFF) Turn-off delay time - - 20 tf Fall time - - 15 VSD Diode forward voltage drop - - -1.8 V VGS = 0V, ISD = -500mA trr Reverse recovery time - 300 - ns VGS = 0V, ISD = -500mA Notes: 2. All A.C. parameters sample tested. P-Channel Switching Waveforms and Test Circuit RGEN Input Pulse Generator VDD RL D.U.T OUTPUT INPUT -10V tr tftd(ON) t(ON) 90% 10% 90% 10% 10% 90% td(OFF) t(OFF) OUTPUT VDD
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888 www.supertex.com TC7920 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-TC7920 B080613 12-Lead DFN Package Outline (K6) 4.00x4.00mm body, 1.00mm height (max), 0.50mm pitch Symbol A A1 A3 b D D2 E E2 e L L1 θ Dimension (mm) MIN 0.80 0.00 0.20 REF 0.50 BSC 0.30 0.00 0O Drawings not to scale. Supertex Doc.#: DSPD-12DFNK64X4P050, Version A030210. Seating Plane θ Top View Side View Bottom View A D E eb A3 L V iew B View B Note 1 (Index Area D/2 x E/2) Note 3 Note 2 Note 1 (Index Area D/2 x E/2) Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square.