TC6215

TC6215 SUTEX | Alldatasheet

Document overview

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Technical content

Features

Back to back gate-source Zener diodes Guaranteed RDS(ON) at 4.0V gate drive Low threshold Low on-resistance Independent N- and P-channels Electrically isolated N- and P-channels Low input capacitance Fast switching speeds Free from secondary breakdowns Low input and output leakage

Applications

Amplifiers Buffers Piezoelectric transducer drivers General purpose line drivers Logic level interfaces General Description The Supertex TC6215 consists of high voltage, low threshold N-channel and P-channel MOSFETs in an 8-Lead SOIC (TG) package. Both MOSFETs have integrated back to back gate-source Zener diode clamps and guaranteed R DS(ON) ratings down to 4.0V gate drive allowing them to be driven directly with standard 5.0V CMOS logic. These low threshold enhancement-mode (normally-off) transistors utilize an advanced vertical DMOS structure and Supertex’s well-proven silicon- gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally-induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. N- and P-Channel Enhancement-Mode Dual MOSFET -G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Parameter Value Drain-to-source voltage BVDSS Drain-to-gate voltage BVDGS Gate-to-source voltage ±20V Operating and storage temperature -55°C to + 150°C Soldering temperature* 300°C Device Package Option BVDSS/BVDGS RDS(ON) (Max) 8-Lead SOIC 4.90x3.90mm body 1.75mm height (max) 1.27mm pitch N-Channel (V) P-Channel (V) N-Channel (Ω) P-Channel (Ω) TC6215 TC6215TG-G 150 -150 4.0 7.0

Ordering Information

YY = Year Sealed WW = Week Sealed L = Lot Number = “Green” Packaging YYWW C6215 L L L L 8-Lead SOIC (TG) (top view) Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. * Distance of 1.6mm from case for 10 seconds. 8-Lead SOIC (TG) Package may or may not include the following marks: Si or Pin Configuration

• 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Sym Parameter Min Typ Max Units Conditions BVDSS Drain-to-source breakdown voltage 150 - - V VGS = 0V, ID = 1.0mA VGS(th) Gate threshold voltage 1.0 - 2.0 V VGS = VDS, ID =1.0mA ΔVGS(th) Change in VGS(th) with temperature - - -4.5 mV/OC VGS = VDS, ID = 1.0mA VZGS Gate-source back to back Zener voltage ±14 - ±25 V IGS = ±1.0mA IDSS Zero gate voltage drain current - - 5.0 µA VGS = 0V, VDS = Max Rating - - 1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125°C ID(ON) On-state drain current - 2.0 - A VGS = 4.5V, VDS = 25V - 3.8 - VGS = 10V, VDS = 25V RDS(ON) Static drain-to-source on-state resistance - - 4.0 Ω VGS = 4.0V, ID = 0.5A - - 4.0 VGS = 10V, ID = 2.0A ΔRDS(ON) Change in RDS(ON) with temperature - - 1.0 %/OC VGS = 5.0V, ID = 2.0A GFS Forward transconductance 560 - - mmho VDS = 10V, ID = 0.5A CISS Input capacitance - 120 - pF VGS = 0V, VDS = 25V, f = 1.0MHz COSS Common source output capacitance - 33 - CRSS Reverse transfer capacitance - 11 - td(ON) Turn-on delay time - 2.5 - ns VDD = 25V, ID = 1.0A, RGEN = 25Ω tr Rise time - 2.3 - td(OFF) Turn-off delay time - 17.2 - tf Fall time - 11.3 - VSD Diode forward voltage drop - - 1.4 V VGS = 0V, ISD = 0.5A trr Reverse recovery time - 90 - ns VGS = 0V, ISD = 0.5A N-Channel Switching Waveforms and Test Circuit RGEN Input Pulse Generator VDD RL D.U.T. OUTPUT 10V VDD td(OFF) Input Output tr tftd(ON) t(ON) t(OFF) 10% 90% 90% 10% 90% 10% N-Channel Electrical Characteristics (TA = 25°C unless otherwise specified) Notes: All DC parameters 100% tested at 25°C unless otherwise stated. (Pulsed test: 300µs pulse at 2% duty cycle.) All AC parameters sample tested.

• 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com P-Channel Switching Waveforms and Test Circuit RGEN Input Pulse Generator VDD RL D.U.T. OUTPUT -10V VDD td(OFF) Input Output tr tftd(ON) t(ON t(OFF) 90% 10% 90% 10% 10% 90% P-Channel Electrical Characteristics (TA = 25°C unless otherwise specified) Sym Parameter Min Typ Max Units Conditions BVDSS Drain-to-source breakdown voltage -150 - - V VGS = 0V, ID = -1.0mA VGS(th) Gate threshold voltage -1.0 - -2.0 V VGS = VDS, ID =-1.0mA ΔVGS(th) Change in VGS(th) with temperature - - 4.5 mV/OC VGS = VDS, ID = -1.0mA VZGS Gate-source back to back Zener voltage ±14 - ±25 V IGS = ±1.0mA IDSS Zero gate voltage drain current - - -5.0 µA VGS = 0V, VDS = Max Rating - - -1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125°C ID(ON) On-state drain current - -1.5 - A VGS = -4.5V, VDS = -25V - -3.0 - VGS = -10V, VDS = -25V RDS(ON) Static drain-to-source on-state resistance - - 7.5 Ω VGS = -4.0V, ID = -0.25A ΔRDS(ON) Change in RDS(ON) with temperature - - 1.0 %/OC VGS = -5.0V, ID = -0.25A GFS Forward transconductance 290 - - mmho VDS = -10V, ID = -0.25A CISS Input capacitance - 127 - pF VGS = 0V, VDS = -25V, f = 1.0MHz COSS Common source output capacitance - 29 - CRSS Reverse transfer capacitance - 9.0 - td(ON) Turn-on delay time - 2.4 - ns VDD = -25V, ID = -1.0A, RGEN = 25Ω tr Rise time - 2.3 - td(OFF) Turn-off delay time - 16.2 - tf Fall time - 11.1 - VSD Diode forward voltage drop - - -1.4 V VGS = 0V, ISD = -0.25A trr Reverse recovery time - 80 - ns VGS = 0V, ISD = -0.25A Notes: All DC parameters 100% tested at 25°C unless otherwise stated. (Pulsed test: 300µs pulse at 2% duty cycle.) All AC parameters sample tested.

• 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Block Diagram SN GN SP GP DP DP DN DN N-Channel P-Channel 8-Lead SOIC (top view) P-Channel Output Characteristics -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 VDS (volts) ID (amperes) VGS=-10V VGS=-8V VGS=-7V VGS=-6V VGS=-5V VGS=-4V VGS=-3V VGS=-2V P-Channel Saturation Characteristics -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 VDS (volts) ID (amperes) VGS=-10V VGS=-8V VGS=-6V VGS=-5V VGS=-4V VGS=-3V VGS=-2V N-Channel Output Characteristics 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 5 10 15 20 25 30 35 40 45 50 VDS (volts) ID (amperes) VGS =10V VGS =8V VGS =7V VGS =6V VGS =5V VGS =4V VGS =3V VGS=2V N-Channel Saturation Characteristics 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 1 2 3 4 5 6 7 8 9 1 0 VDS (volts) ID (amperes) VGS=10V VGS=8V VGS=6V VGS=5V VGS=4V VGS=3V VGS=2V Typical Performance Curves

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications ©2008 All rights reserved. Unauthorized use or reproduction is prohibited .

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888 www.supertex.com TC6215 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-TC6215 A122208 8-Lead SOIC (Narrow Body) Package Outline (TG) 4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch Seating Plane Gauge Plane L E D e b A A2 Seating Plane A A Top View Side View View B View B θ Note 1 (Index Area D/2 x E1/2) View A-A h h Note 1 Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1 Dimension (mm) 1.27 BSC 0.25 0.40 1.04 REF 0.25 BSC 0O 5O JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005. * This dimension is not specified in the original JEDEC drawing. The value listed is for reference only. Drawings are not to scale. Supertex Doc. #: DSPD-8SOLGTG, Version H101708. Note: This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator.