TC1550 SUTEX | Alldatasheet
Document overview
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Technical content
Features
Independent N- and P-channels Electrically isolated N- and P-channels Low input capacitance Fast switching speeds Free from secondary breakdowns Low input and output leakage
Applications
Amplifi ers Buffers Piezoelectric transducer drivers General purpose line drivers General Description The Supertex TC1550TG-G consists of a high voltage N- channel and P-channel MOSFET in an SO-8 package. These are enhancement-mode (normally-off) transistors utilizing an advanced vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coeffi cient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. N- and P-Channel Enhancement-Mode Dual MOSFET Typical Application Circuit VDD2 VHVDD1 Supertex MD1210K6 VLVSS2VSS1GND OUTA OUTB INA INB OE 0.47µF +12V 3.3V CMOS Logic Inputs Supertex TC1550TG +250V -250V Piezoelectric Transducer 10nF 250V 10nF 250V 15V 15V
-G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Parameter Value Drain-to-source voltage BV DSS Drain-to-gate voltage BV DGS Gate-to-source voltage ±20V Operating and storage temperature -55°C to + 150°C Soldering temperature 1 300°C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Note: 1. Distance of 1.6mm from case for 10 seconds. Device BVDSS/BVDGS RDS(ON) (Max) Package Option N-Channel P-Channel N-Channel P-Channel 8-Lead SO TC1550 500V -500V 60Ω 125Ω TC1550TG-G Pin Confi guration
Ordering Information
(Top View) N-Channel P-Channel N-Channel Electrical Characteristics (TA = 25°C unless otherwise specifi ed) Symbol Parameter Min Typ Max Units Conditions BVDSS Drain-to-Source Breakdown Voltage 500 - - V V GS = 0V, ID = 1mA VGS(th) Gate Threshold Voltage 2.0 - 4.0 V V GS = VDS, ID =1mA ΔVGS(th) Change in VGS(th) with Temperature - -3.8 -5.0 mV/ OCV GS = VDS, ID = 1mA IGSS Gate Body Leakage Current - - 100 nA V GS = ±20V, VDS = 0V IDSS Zero Gate Voltage Drain Current -- 1 0 µ A V GS = 0V, VDS = Max Rating - - 1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125°C ID(ON) On-State Drain Current - 100 - mA VGS = 5.0V, VDS = 25V 150 350 - V GS = 10V, VDS = 25V RDS(ON) Static Drain-to-Source ON-State Resistance -4 5- Ω VGS = 5.0V, ID = 50mA -4 0 6 0 V GS = 10V, ID = 50mA ΔRDS(ON) Change in RDS(ON) with Temperature - 1.0 1.7 %/ OCV GS = 10V, ID = 50mA GFS Forward Transconductance 50 100 - mmho V DS = 25V, ID =50mA
N-Channel Electrical Characteristics (cont.) Symbol Parameter Min Typ Max Units Conditions CISS Input Capacitance - 45 55 pF VGS = 0V, VDS = 25V, f = 1MHz COSS Common Source Output Capacitance - 8.0 10 CRSS Reverse Transfer Capacitance - 2.0 5.0 td(ON) Turn-ON Delay Time - - 10 ns VDD = 25V, ID = 150mA, RGEN = 25Ω tr Rise Time - - 15 td(OFF) Turn-Off Delay Time - - 10 tf Fall Time - - 10 VSD Diode Forward Voltage Drop - 0.8 - V V GS = 0V, ISD = 500mA trr Reverse Recovery Time - 300 - ns V GS = 0V, ISD = 500mA Symbol Parameter Min Typ Max Units Conditions BVDSS Drain-to-SourceBreakdown Voltage -500 - - V V GS = 0V, ID = -1mA VGS(th) Gate Threshold Voltage -2.0 - -4.5 V V GS = VDS, ID = -1mA ΔVGS(th) Change in VGS(th) with Temperature - 3.5 6.0 mV/ OCV GS = VDS, ID = -1mA IGSS Gate Body Leakage Current - - 100 nA V GS = ±20V, VDS = 0V IDSS Zero Gate Voltage Drain Current -- - 1 0 µ A V GS = 0V, VDS = Max Rating -- - 1 . 0 m A VDS = 0.8 Max Rating, VGS = 0V, TA = 125°C ID(ON) On-State Drain Current -- 9 0- mA VGS = -5.0V, VDS = -25V -100 -240 - V GS = -10V, VDS = -25V RDS(ON) Static Drain-to-Source ON-State Resistance -8 5- Ω VGS = -5.0V, ID = -5.0mA -8 0 1 2 5 V GS = -10V, ID = -10mA ΔRDS(ON) Change in RDS(ON) with Temperature - 0.85 - %/ OCV GS = -10V, ID = -10mA GFS Forward Transconductance 25 40 - mmho V DS = -25V, ID = -10mA CISS Input Capacitance - 40 70 pF VGS = 0V, VDS = -25V, f = 1MHz COSS Common Source Output Capacitance - 10 20 CRSS Reverse Transfer Capacitance - 3.0 10 td(ON) Turn-ON Delay Time - 5.0 10 ns VDD = -25V, ID = -100mA, RGEN = 25Ω tr Rise Time - 8.0 10 td(OFF) Turn-Off Delay Time - 8.0 15 tf Fall Time - 5.0 16 VSD Diode Forward Voltage Drop - -0.8 -1.5 V V GS = 0V, ISD = -100mA trr Reverse Recovery Time - 200 - ns V GS = 0V, ISD = -100mA P-Channel Electrical Characteristics (TA = 25°C unless otherwise specifi ed) Notes: (1) All DC parameters 100% tested at 25°C unless otherwise stated. (Pulsed test: 300µs pulse at 2% duty cycle.) (2) All AC parameters sample tested.
P-Channel Switching Waveforms and Test Circuit RGEN Input Pulse Generator VDD RL D.U.T. OUTPUT -10V VDD td(OFF) Input Output tr tftd(ON) t(ON t(OFF) 90% 10% 90% 10% 10% 90% N-Channel Switching Waveforms and Test Circuit RGEN Input Pulse Generator VDD RL D.U.T. OUTPUT 10V VDD td(OFF) Input Output tr tftd(ON) t(ON) t(OFF) 10% 90% 90% 10% 90% 10%
Doc.# DSFP-TC1550 NR011707 TC1550 (The package drawing(s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) 8-Lead SO (TG) Package Outline 45° 5° - 15° (4 PLCS) 4.90 ± 0.10 1.27BSC 6.00 ± 0.20 3.90 ± 0.10 Notes: 1. All dimensions in millimeters. Angles in degrees. 2. If the corner is not chamfered, then a Pin 1 identifier must be located within the area indicated. Note 2
1.75 MAX
1.25 MIN
0.25 - 0.50 0° - 8° 0.40 - 1.27 0.17 - 0.25 Top View Side View End View Note 2