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www.ablicinc.com 3-WIRE SERIAL E2PROM © ABLIC Inc., 2016 Rev.1.1_01 This IC is a high speed, low current consumption, 3-wire serial E2PROM with a wide operating voltage range. This IC has the capacity of 1 K-bit, 2 K-bit, 4 K-bit, 8 K-bit and 16 K-bit, and the organization is 64 words 16-bit, 128 words 16-bit, 256 words 16-bit, 512 words 16-bit and 1024 words 16-bit, respectively. Sequential read is available, at which time addresses are automatically incremented in 16-bit blocks. The communication method is by the Microwire bus. Caution This product is intended to use in general electronic devices such as consumer electronics, office equipment, and communications devi ces. Before using the product in me dical equipment or automobile equipment including car audio, keyless entry and engine control unit, contact to ABLIC Inc. is indispensable. Features Memory capacity S-93C46C: 1 K-bit (64-word 16-bit) S-93C56C: 2 K-bit (128-word 16-bit) S-93C66C: 4 K-bit (256-word 16-bit) S-93C76C: 8 K-bit (512-word 16-bit) S-93C86C: 16 K-bit (1024-word 16-bit) Operation voltage range Read: 1.6 V to 5.5 V Write: 1.8 V to 5.5 V Operation frequency: 2.0 MHz max. Write time: 4.0 ms max. Sequential read Write protect function duri ng the low power supply voltage Function to protect against write due to erroneous instruction recognition Endurance: 106 cycle / word*1 (Ta = 85C) Data retention: 100 years (Ta = 25C) 50 years (Ta = 85C) Initial delivery state: FFFFh Operation temperat ure range: Ta = 40°C to 85°C Lead-free (Sn 100%), halogen-free *1. For each address (Word: 16-bit) Packages 8-Pin SOP (JEDEC) 8-Pin TSSOP TMSOP-8 SNT-8A 8 4 www.ablic.com
S-93C46C/56C/66C/76C/86C Rev.1.1_01 Block Diagram Memory array Data register Address decoder Mode decode logic Clock pulse monitoring circuit Output buffer VCC GND DO DI CS Clock generator Voltage detector SK
Rev.1.1_01 S-93C46C/56C/66C/76C/86C Product Name Structure 1. Product name S-93CxxC x 0 I - xxxx U 3 Environmental code U: Lead-free (Sn 100%), halogen-free Package abbreviation and IC packing specification J8T1: 8-Pin SOP (JEDEC), Tape T8T1: 8-Pin TSSOP, Tape K8T3: TMSOP-8, Tape I8T1: SNT-8A, Tape Operation temperature I: Ta = 40C to 85C Fixed Pin assignment D: 8-Pin SOP (JEDEC) 8-Pin TSSOP TMSOP-8 SNT-8A R: 8-Pin SOP (JEDEC) (Rotated) Product name S-93C46C: 1 K-bit S-93C56C: 2 K-bit S-93C66C: 4 K-bit S-93C76C: 8 K-bit S-93C86C: 16 K-bit *1. Refer to the tape drawing *2. S-93C46C/56C/66C only 2. Packages Package Name Dimension Tape Reel Land 8-Pin SOP (JEDEC) FJ008-Z-P-SD FJ008-Z-C-SD FJ008-Z-R-SD 8-Pin TSSOP FT008-Z-P-SD FT008-Z-C-SD FT008-Z-R-SD TMSOP-8 FM008-A-P-SD FM008-A-C-SD FM008-A-R-SD SNT-8A PH008-A-P-SD PH008-A-C-SD PH008-A-R-SD PH008-A-L-SD
S-93C46C/56C/66C/76C/86C Rev.1.1_01 3. Product name list Product Name Capacity Package Name S-93C46CD0I-J8T1U3 1 K-bit 8-Pin SOP (JEDEC) S-93C46CR0I-J8T1U3 1 K-bit 8-Pin SOP (JEDEC) (Rotated) S-93C46CD0I-T8T1U3 1 K-bit 8-Pin TSSOP S-93C46CD0I-K8T3U3 1 K-bit TMSOP-8 S-93C46CD0I-I8T1U3 1 K-bit SNT-8A S-93C56CD0I-J8T1U3 2 K-bit 8-Pin SOP (JEDEC) S-93C56CR0I-J8T1U3 2 K-bit 8-Pin SOP (JEDEC) (Rotated) S-93C56CD0I-T8T1U3 2 K-bit 8-Pin TSSOP S-93C56CD0I-K8T3U3 2 K-bit TMSOP-8 S-93C56CD0I-I8T1U3 2 K-bit SNT-8A S-93C66CD0I-J8T1U3 4 K-bit 8-Pin SOP (JEDEC) S-93C66CR0I-J8T1U3 4 K-bit 8-Pin SOP (JEDEC) (Rotated) S-93C66CD0I-T8T1U3 4 K-bit 8-Pin TSSOP S-93C66CD0I-K8T3U3 4 K-bit TMSOP-8 S-93C66CD0I-I8T1U3 4 K-bit SNT-8A S-93C76CD0I-J8T1U3 8 K-bit 8-Pin SOP (JEDEC) S-93C76CD0I-T8T1U3 8 K-bit 8-Pin TSSOP S-93C76CD0I-K8T3U3 8 K-bit TMSOP-8 S-93C76CD0I-I8T1U3 8 K-bit SNT-8A S-93C86CD0I-J8T1U3 16 K-bit 8-Pin SOP (JEDEC) S-93C86CD0I-T8T1U3 16 K-bit 8-Pin TSSOP S-93C86CD0I-K8T3U3 16 K-bit TMSOP-8 S-93C86CD0I-I8T1U3 16 K-bit SNT-8A
Rev.1.1_01 S-93C46C/56C/66C/76C/86C Pin Configuration 1. 8-Pin SOP (JEDEC) Top view Pin No. Symbol Description
1 CS Chip select input
2 SK Serial clock input
3 DI Serial data input
4 DO Serial data output
5 GND Ground
6 TEST*1 Test
7 NC No connection
8 VCC Power supply
- 8-Pin SOP (JEDEC) (Rotated) Top view Pin No. Symbol Description
1 NC No connection
2 VCC Power supply
3 CS Chip select input
4 SK Serial clock input
5 DI Serial data input
6 DO Serial data output
7 GND Ground
8 TEST*1 Test
- 8-Pin TSSOP Top view Pin No. Symbol Description
*1. Connect to GND or the VCC pin, or se t to open. Even if this pin is not c onnected, performance is not affected so long as the absolute maximum rating is not exceeded.
S-93C46C/56C/66C/76C/86C Rev.1.1_01 4. TMSOP-8 Top view Pin No. Symbol Description
- SNT-8A Top view Pin No. Symbol Description
*1. Connect to GND or the VCC pin, or se t to open. Even if this pin is not c onnected, performance is not affected so long as the absolute maximum rating is not exceeded.
Rev.1.1_01 S-93C46C/56C/66C/76C/86C Absolute Maximum Ratings Table 1 Item Symbol Absolute Maximum Rating Unit Power supply voltage V CC 0.3 to 6.5 V Input voltage V IN 0.3 to 6.5 V Output voltage V OUT 0.3 to VCC 0.3 V Operation ambient temperature T opr 40 to 85 °C Storage temperature T stg 65 to 150 °C Caution The absolute maximum ra tings are rated values exceeding whic h the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Recommended Operating Conditions Table 2 Item Symbol Condition Ta = 40C to 85C Unit Min. Max. Power supply voltage V CC READ, EWDS 1.6 5.5 V WRITE, ERASE,EWEN 1.8 5.5 V WRAL, ERAL 2.5 5.5 V High level input voltage V IH VCC = 4.5 V to 5.5 V 2.0 V CC V VCC = 2.7 V to 4.5 V 0.8 VCC V CC V VCC = 1.6 V to 2.7 V 0.8 VCC V CC V Low level input voltage V IL VCC = 4.5 V to 5.5 V 0.0 0.8 V VCC = 2.7 V to 4.5 V 0.0 0.2 VCC V VCC = 1.6 V to 2.7 V 0.0 0.15 VCC V Pin Capacitance Table 3 (Ta = 25°C, f = 1.0 MHz, VCC = 5.0 V) Item Symbol Condition Min. Max. Unit Input capacitance C IN V IN = 0 V 8 pF Output capacitance C OUT V OUT = 0 V 10 pF Endurance Table 4 Item Symbol Operation Ambient Temperature Min. Max. Unit Endurance NW Ta = 40°C to 85°C 10 6 cycle / word*1 *1. For each address (Word: 16-bit) Data Retention Table 5 Item Symbol Operation Ambient Temperature Min. Max. Unit Data retention Ta = 25°C 100 year Ta = 40°C to 85°C 50 year
S-93C46C/56C/66C/76C/86C Rev.1.1_01 DC Electrical Characteristics Table 6 Item Symbol Condition Ta = 40C to 85C UnitVCC = 1.6 V to 1.8 V, fSK = 0.5 MHz VCC = 1.8 V to 2.5 V, fSK = 1.0 MHz VCC = 2.5 V to 4.5 V, fSK = 2.0 MHz VCC = 4.5 V to 5.5 V, fSK = 2.0 MHz Current consumption (read) I CC1 No load at DO pin 0.4 0.4 0.5 0.8 mA Table 7 Item Symbol Condition Ta = 40°C to 85°C UnitVCC = 1.8 V to 4.5 V V CC = 4.5 V to 5.5 V Min. Max. Min. Max. Current consumption (write) I CC2 No load at DO pin 2.0 2.0 mA Table 8 Item Symbol Condition Ta = 40°C to 85°C Standby current consumption ISB CS = GND, DO = Open, Other input pins are V CC or GND Input leakage current I LI CS, SK, DI, VIN = GND to VCC 1.0 1.0 1.0 A Output leakage current ILO DO, VOUT = GND to VCC 1.0 1.0 1.0 A Pull-down current I PD TEST, VIN = GND ~ VCC 1.2 1.2 1.2 A Low level output voltage VOL IOL = 2.1 mA 0.4 V IOL = 100 A 0.1 0.1 0.1 V High level output voltage VOH IOH = 100 A VCC 0.3 VCC 0.3 V IOH = 10 A VCC 0.2 VCC 0.2 VCC 0.2 V Data hold voltage of write enable latch VDH Only program disable mode 1.5 1.5 1.5 V
Rev.1.1_01 S-93C46C/56C/66C/76C/86C AC Electrical Characteristics Table 9 Measurement Conditions Input pulse voltage 0.1 VCC to 0.9 VCC Output reference voltage 0.5 VCC Output load 100 pF Table 10 Item Symbol Ta = 40°C to 85°C CS pin setup time t CSS 0.4 0.2 0.15 0.15 s CS pin hold time t CSH 0 0 0 0 s CS pin deselect time t CDS 0.4 0.2 0.2 0.2 s Data setup time t DS 0.2 0.1 0.1 0.1 s Data hold time t DH 0.2 0.1 0.1 0.1 s Output delay time t PD 0.8 0.6 0.25 0.25 s Clock frequency*1 fSK 0 0.5 0 1.0 0 2.0 0 2.0 MHz SK clock time "L"*1 tSKL 0.5 0.2 0.2 0.1 s SK clock time "H"*1 tSKH 0.5 0.2 0.2 0.1 s Output disable time t HZ1, tHZ2 0 0.5 0 0.2 0 0.2 0 0.15 s Output enable time t SV 0 0.5 0 0.2 0 0.2 0 0.15 s Write time t PR 4.0 4.0 4.0 4.0 ms *1. The clock cycle of the SK clock (frequency f SK) is 1/f SK s. This clock cycle is determined by a combination of several AC characteristics. Note that the clock cycle cannot be set as (1/fSK) = tSKL (min.) tSKH (min.) by minimizing the SK clock cycle time. t SKH t CDS t CSS CS Valid dataValid data DI t SKL SK t SV t HZ2 t CSH t HZ1 t PD t PD t DS t DHt DS t DH High-Z High-Z High-Z DO DO (READ) (VERIFY) High-Z*1 1/fSK *1. Indicates high impedance. *2. 1/f SK is the SK clock cycle. This clock cycle is determined by a combination of several AC characteristics. Note that the clock cycle cannot be set as (1/f SK) = t SKL (min.) tSKH (min.) by minimizing the SK clock cycle time. Figure 1 Timing Chart
S-93C46C/56C/66C/76C/86C Rev.1.1_01 Pin Functions 1. CS (chip select input) pin This is an input pin to set a chip in the select status. In t he "L" input level, this IC is in the non-select status and its output is "High-Z". This IC is in standby as long as it is not in write inside. Th is IC goes in active by setting the chip select to "H". Input any instruction code after power-on and a rising of chip select. 2. SK (serial clock input) pin This is a clock input pin to set the timing of serial dat a. A start bit, an operation code, an address and a write data are received at a rising edge of clock. Data is output during rising edge of clock. 3. DI (serial data input) pin This pin is to input serial data. This pin receives a start bit, an operation code, an addr ess and a write data. This pin latches data at rising edge of serial clock. 4. SO (serial data output) pin This pin is to output serial data. The data output changes at rising edge of serial clock. 5. TEST (test input) pin This is an input pin in test mode. C onnect to GND or the VCC pin, or set to open. Because this pin has a built-in pull-down element, pull-down current flows when it connected to VCC pin. Initial Delivery State Initial delivery state of all addresses is "FFFFh".
Rev.1.1_01 S-93C46C/56C/66C/76C/86C Instruction Sets 1. S-93C46C Table 11 Instruction Start Bit Operation Code Address Data SK input clock 1 2 3 4 5 6 7 8 9 10 to 25 READ (Data read) 1 1 0 A5 A4 A3 A2 A1 A0 D15 to D0 output*1 WRITE (Data write) 1 0 1 A5 A4 A3 A2 A1 A0 D15 to D0 input ERASE (Data erase) 1 1 1 A5 A4 A3 A2 A1 A0 WRAL (Chip write) 1 0 0 0 1 x x x x D15 to D0 input ERAL (Chip erase) 1 0 0 1 0 x x x x EWEN (Write enable) 1 0 0 1 1 x x x x EWDS (Write disable) 1 0 0 0 0 x x x x *1. When the 16-bit data in the s pecified address has been output, the data in the next address is output. Remark x = Don't care. 2. S-93C56C Table 12 Instruction Start Bit Operation Code Address Data SK input clock 1 2 3 4 5 6 7 8 9 10 11 12 to 27 READ (Data read) 1 1 0 x A6 A5 A4 A3 A2 A1 A0 D15 to D0 output*1 WRITE (Data write) 1 0 1 x A6 A5 A4 A3 A2 A1 A0 D15 to D0 input ERASE (Data erase) 1 1 1 x A6 A5 A4 A3 A2 A1 A0 WRAL (Chip write) 1 0 0 0 1 x x x x x x D15 to D0 input ERAL (Chip erase) 1 0 0 1 0 x x x x x x EWEN (Write enable) 1 0 0 1 1 x x x x x x EWDS (Write disable) 1 0 0 0 0 x x x x x x *1. When the 16-bit data in the s pecified address has been output, the data in the next address is output. Remark x = Don't care. 3. S-93C66C Table 13 Instruction Start Bit Operation Code Address Data SK input clock 1 2 3 4 5 6 7 8 9 10 11 12 to 27 READ (Data read) 1 1 0 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 output*1 WRITE (Data write) 1 0 1 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 input ERASE (Data erase) 1 1 1 A7 A6 A5 A4 A3 A2 A1 A0 WRAL (Chip write) 1 0 0 0 1 x x x x x x D15 to D0 input ERAL (Chip erase) 1 0 0 1 0 x x x x x x EWEN (Write enable) 1 0 0 1 1 x x x x x x EWDS (Write disable) 1 0 0 0 0 x x x x x x *1. When the 16-bit data in the s pecified address has been output, the data in the next address is output. Remark x = Don't care.
S-93C46C/56C/66C/76C/86C Rev.1.1_01 4. S-93C76C Table 14 Instruction Start Bit Operation Code Address Data SK input clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 to 29 READ (Data read) 1 1 0 x A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 output *1 WRITE (Data write) 1 0 1 x A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 input ERASE (Data erase) 1 1 1 x A8 A7 A6 A5 A4 A3 A2 A1 A0 WRAL (Chip write) 1 0 0 0 1 x x x x x x x x D15 to D0 input ERAL (Chip erase) 1 0 0 1 0 x x x x x x x x EWEN (Write enable) 1 0 0 1 1 x x x x x x x x EWDS (Write disable) 1 0 0 0 0 x x x x x x x x *1. When the 16-bit data in the s pecified address has been output, the data in the next address is output. Remark x = Don't care. 5. S-93C86C Table 15 Instruction Start Bit Operation Code Address Data SK input clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 to 29 READ (Data read) 1 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 output *1 WRITE (Data write) 1 0 1 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 input ERASE (Data erase) 1 1 1 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 WRAL (Chip write) 1 0 0 0 1 x x x x x x x x D15 to D0 input ERAL (Chip erase) 1 0 0 1 0 x x x x x x x x EWEN (Write enable) 1 0 0 1 1 x x x x x x x x EWDS (Write disable) 1 0 0 0 0 x x x x x x x x *1. When the 16-bit data in the s pecified address has been output, the data in the next address is output. Remark x = Don't care.
Rev.1.1_01 S-93C46C/56C/66C/76C/86C Operation All instructions are executed by inputting the DI pin in synchronization with the rising of the SK pulse after the CS pin goes to "H". An instruction set is input in the order of start bit, instruction, address, and data. Instruction input finishes when the CS pin goes to "L". "L" must be input to the CS pin between commands during t CDS. While "L" is being input to the CS pin, this IC is in st andby mode, so the SK pin and the DI pin inputs are invalid and no instructions are allowed. 1. Start Bit A start bit is recognized when the DI pin goes to "H" at the rising of the SK pulse after the CS pin goes to "H". After the CS pin goes to "H", a start bit is not recognized even if the SK pulse is input as long as the DI pin is "L". 1. 1 Dummy clock The SK clocks input while the DI pin is "L" before a start bit is input are called dummy clocks. Dummy clocks are effective when aligning the number of in struction sets (clocks) sent by the CPU with those required for serial memory operation. For example, when the CPU instruction set is 16 bits, the number of instruction set clocks can be adjusted by inserting the 7-bit dummy clock in S- 93C46C, the 5-bit dummy clock in S-93C56C/66C and the 3-bit dummy clock in S-93C76C/86C. 1. 2 Start bit input failure (1) When the output of the DO pin is "H" during the verify period after a write operation, if "H" is input to the DI pin at the rising of the SK pulse, this IC recognizes that a start bit has been input. To prevent this failure, input "L" to the DI pin during the verify operation period (refer to " 3. 1 Verify operation "). (2) When a 3-wire interface is configured by connecting t he DI input pin and the DO out put pin, a period in which the data output from the CPU and the serial memory collide may be generated, preventing successful input of the start bit. Take the measures described in " 3-Wire Interface (Direct Connection between DI Pin and DO Pin )". 2. Reading (READ) The READ instruction reads data from a specified address. After the CS pin goes to "H", input an in struction in the order of the start bit, read instruct ion, and address. Since the last input address (A0) has been latched, the output status of the DO pi n changes from "High-Z" to "L", which is held until the next rising of the SK pulse. 16-bi t data starts to be output in synchroni zation with the next rising of the SK pulse. 2. 1 Sequential read After the 16-bit data at the specif ied address has been output, inputting the SK pulse while the CS pin is "H" automatically increments t he address, and causes the 16- bit data at the next addre ss to be output sequentially. The above method makes it possible to read the data in the whole memory space. The last address (A n A 1 A0 = 1 1 1) rolls over to the top address (A n A 1 A0 = 0 0 0).
Rev.1.1_01 S-93C46C/56C/66C/76C/86C 3. Writing (WRITE, ERASE, WRAL, ERAL) A write operation includes four write instructions: data wr ite (WRITE), data erase (ER ASE), chip write (WRAL), and chip erase (ERAL). A write instruction (WRITE, ERASE, WRAL, ERAL) starts a write operation to the memory cell when "L" is input to the CS pin after a specified number of clocks have been input. The SK pin and the DI pin i nputs are invalid during the write period, so do not input an instruction. Input an instruction while the output status of the DO pin is "H" or "High-Z". A write operation is valid only in program enable mode (refer to "4. Write enable (EWEN) / write disable (EWDS)"). 3. 1 Verify operation A write operation executed by any instruction is completed within 4 ms (write time t PR), so if the completion of the write operation is recognized, the write cycle can be minimized. A sequent ial operation to confi rm the status of a write operation is called a verify operation. 3. 1. 1 Operation method After the write operation has started (CS pin = "L"), the status of the write operation can be verified by confirming the output status of the DO pin by inputting "H" to the CS pin again. This sequence is called a verify operation, and the period that "H" is input to the CS pin after the wr ite operation has started is called the verify operation period. The relationship between the output st atus of the DO pin and the write operation duri ng the verify operation period is as follows. (1) DO pin = "L": Writing in progress (busy) (2) DO pin = "H": Writing completed (ready) 3. 1. 2 Operation example There are two methods to perform a verify operation: Wa iting for a change in the out put of the DO pin while keeping the CS pin "H", or suspending the verify operation (CS pin = "L ") once and then performing it again to verify the output of the DO pin. The latter method allows the CPU to perform other processing during the wait period, allowing an efficient system to be designed. Caution 1. Input "L" to the DI pin during a verify operation. 2. If "H" is input to the DI pin at the rising of the SK pulse when the output status of the DO pin is "H", this IC latches the instru ction assuming that a start bit h as been input. In this case, note that the DO pin immediately enters "High-Z".
Rev.1.1_01 S-93C46C/56C/66C/76C/86C Write Protect Function during the Low Power Supply Voltage This IC provides a built-in detection circuit to detect a low power supply voltage. When the power supply voltage is low or at power-on, the write inst ructions (WRITE, ERASE, WRAL, and ERAL) are cancelled, and the write disable (EWDS) status is automatically set. The detection voltage and the release voltage are 1.2 V typ. (refer to Figure 20). Therefore, when a write oper ation is performed after the power suppl y voltage has dropped and then risen again up to the level at which writing is possible, a write enable instruction (EWEN) must be sent before a write instruction (WRITE, ERASE, WRAL, or ERAL) is executed. When the power supply voltage drops during a write operation, t he data being written to an addre ss at that time is not guaranteed. Write instructions are cancelled Write disable status (EWDS) is automatically set Release voltage (VDET) 1.2 V typ. Power supply voltage Detection voltage (VDET) 1.2 V typ. Figure 20 Operation during the Low Power Supply Voltage
S-93C46C/56C/66C/76C/86C Rev.1.1_01 Function to Protect Against Write due to Erroneous Instruction Recognition This IC provides a built-in clock pulse monitoring circui t which is used to prevent an erroneous write operation by canceling write instructions (WRI TE, ERASE, WRAL, and ERAL) recognized erroneously due to an erroneous clock count caused by the application of noise pulses or double counting of clocks. In structions are cancelled if a clock pulse whose count other than the one specified for each write instruction (WRITE, ERASE, WRAL, or ERAL) is detected. Example: Erroneous Recognition of EWDS as ERASE CS SK DI Input EWDS instruction Erroneous recognition as ERASE instruction due to noise pulse Noise pulse Example of S-93C76C/86C In products that do not incorporate a clock pulse monitoring circuit, "FFFFh" is mistakenly written to address 00h. However the S-93C76C/86C detects the overcount and cancels the instruction without performing a write operation. 1 3 4 5 6 72 1 0 0 0 0 00 1 0 0 0 0 00 10 11 00 1 01 12 13 Figure 21 Example of Clock Pulse Monitoring Circuit Operation
Rev.1.1_01 S-93C46C/56C/66C/76C/86C 2. 2 Output pin DO VCC Figure 26 DO Pin 3. Input pin noise suppression time This IC has a built-in low-pass filter at the SK pin, the DI pin and the CS pin to suppress noise. If the supply voltage is 5.0 V, noise with a pulse width of 20 ns or less at room temperature can be suppressed by the low-pass filter. Note that noise with a pulse width of more than 20 ns is recognized as a pulse since the noise can not be suppressed if the voltage exceeds VIH / VIL. Precautions Do not operate these ICs in excess of the absolute maximum ratings. Attent ion should be paid to the power supply voltage, especially. The surge volt age which exceeds the absolute maxi mum ratings can cause latch-up and malfunction. Perform operations after confirming the detailed operation condition in the data sheet. Operations with moisture on this IC's pins may occu r malfunction by short-circuit between pins. Especially, in occasions like picking this IC up from low temperature tank during the evaluation. Be sure that not remain frost on this IC's pin to prevent malfunction by short-circuit. Also attention should be paid in using on environment, which is easy to dew for the same reason. Do not apply an electrostatic discharge to this IC that ex ceeds the performance ratings of the built-in electrostatic protection circuit. ABLIC Inc. claims no responsibility for any and all disputes arising out of or in connection with any infringement of the products including this IC upon patents owned by a third party.
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Disclaimers (Handling Precautions) 1. All the information described herein (product data, specific ations, figures, tables, programs, algorithms and application circuit examples, et c.) is current as of publishing date of this document and is subject to change without notice. 2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. ABLIC Inc. is not liable for any losses, damages, claims or dem ands caused by the reasons other than the products described herein (hereinafter "the products") or infringement o f third-party intellectual property right and any other right due to the use of the information described herein. 3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described herein. 4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute maximum ratings, operation voltage range and electrical characteristics, etc. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to the use of the products outside their specified ranges. 5. Before using the products, co nfirm their applications, and the laws and regulations of the region or country where they are used and verify suitability, safety and other factors for the intended use. 6. When exporting the products, comply with the Foreign Exchang e and Foreign Trade Act and all other export-related laws, and follow the required procedures. 7. The products are strictly prohibited from using, providing o r exporting for the purposes of the development of weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by any provision or export to the person or entity who i ntends to develop, manufacture, use or store nuclear, biological or chemical weapons or missiles, or use any other military purposes. 8. The products are not designed to be used as part of any devi ce or equipment that may affect the human body, human life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment, aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by ABLIC, Inc. Do not apply the products to the above listed devices and equipments. ABLIC Inc. is not liable for any losses, damages, claims or dem ands caused by unauthorized or unspecified use of the products. 9. In general, semiconductor products may fail or malfunction w ith some probability. The user of the products should therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread prevention measures, and malfunction prevention to prevent acci dents causing injury or death, fires and social damage, etc. that may ensue from the products' failure or malfunction. The entire system in which the products are used must be sufficiently evaluated and judged whether the products are allowed to apply for the system on customer's own responsibility. 10. The products are not designed to be radiation-proof. The ne cessary radiation measures should be taken in the product design by the customer depending on the intended use. 11. The products do not affect human health under normal use. H owever, they contain chemical substances and heavy metals and should therefore not be put in the mouth. The fractu re surfaces of wafers and chips may be sharp. Be careful when handling these with the bare hands to prevent injuries, etc. 12. When disposing of t he products, comply with the laws and ordinances of the country or region where they are used. 13. The information described herein contains copyright informa tion and know-how of ABL IC Inc. The information described herein does not convey any license under any intellec tual property rights or any other rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the inf ormation from this document or any part of this document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express permission of ABLIC Inc. 14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales representative. 15. This Disclaimers have been delivered in a text using the Ja panese language, which text, despite any translations into the English language and the Chinese language, shall be controlling. 2.4-2019.07 www.ablic.com