HDL6M05543

HDL6M05543 ABLIC | Alldatasheet

Document overview

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Technical content

Features

• 0 to ±100V output voltage
• ±2A source and sink peak current for the 1 st high-voltage (HV) pulses (V PP1/VNN1)
• ±2A source and sink peak current with ±1A active clamp for the 2 nd HV pulses (V PP2/VNN2)
• ±2A source and sink peak current for active ground clamp
• 250 Ω (±0.1A) active ground clamp without blo cking diode for anti-leakage (Analog SW type)
• Embedded floating voltage regulators
• Symmetrical positive and negative pulse waveforms for low 2 nd order harmonic distortion
• Up to 200MHz LVDS/LVCMOS clock with 2-bi t edge control (transparent mode available)
• 10 Ω active T/R switch with 2-bit turn-on timing control
• 20MHz output frequency @±60V output, 220pF load
• 1.8V to 5V CMOS logic interface
• Noise-cut diodes at each HV output
• 4-mode output current control for the 2 nd HV rail
• Automatic thermal protection with indicator
• Power-up/down reset function for free power se quencing and for fail-safe in abrupt power drop
• Latch-up free, low crosstalk between channels by SOI CMOS technology
• 64-lead 9x9mm QFN package (RoHS compliant) VNN2 VPP2 VNN1 VPP1 GND GND VFP1 VFP2 bufferbuffer VSS buffer buffer VFN1 VFN2 buffer VDD buffer HVOUT1 <CH1> <CH2> <CH3> <CH4> HVOUT2 HVOUT3 HVOUT4 IN1_0 IN1_1 IN1_2 IN2_0 IN2_1 IN2_2 IN3_0 IN3_1 IN3_2 IN4_0 IN4_1 IN4_2 EN CLKEN CLKB THP Thermal Protection HDL6M05543 VPP2 (0 to +100V) VPP1 (0 to +100V) VDD (+5V) VLL (+1.8 to 5V) GND VSS (-5V) VNN2 (0 to -100V) VNN1 (0 to -100V) VFP2 VFP1 VFP3 VFN1 P1 P2 P4 N1 N2 N4 D-FF 3-to-8 Decoder Logic I/F LVOUT1 LVOUT2 LVOUT3 LVOUT4 CLK CC[1:0] 250Ω GND ASW TRSW 8ΩGND 10Ω CLKIF TXOUT (internal node) TR[1:0] GND 10kΩ CKDL[1:0] VFN3 buffer VFP3 buffer Level Translato r VFN2 VFN3 Floating Voltage Regulators LVDSTM Logic I/F Fig.1 Block diagram

QUAD ±100V 2A TRUE 5-LEVEL ULTRASOUND PULSER HDL6M05543 Rev.2.2_00 1. Absolute Maximum Ratings T A=25°C unless otherwise noted. Table 1 Absolute Maximum Ratings No. Items Symbol Value Units Condition 1 Logic supply voltage V LL -0.4 to +7 V 2 Positive supply voltage V DD -0.4 to +7 V 3 Negative supply voltage V SS -7 to +0.4 V 4 Positive high-voltage supplies V PP1, VPP2 -0.5 to +105 V 5 Negative high-voltage supplies V NN1, VNN2 -105 to +0.5 V

6 Positive high-voltage difference (V PP1-VPP2) -105 to +105 V

7 Negative high-voltage difference (V NN1-VNN2) -105 to +105 V

8 High-voltage outputs (x=1~4) HV OUTx -105 to +105 V

9 Low-voltage outputs (x=1~4) LV OUTx -1 to +1 V

10 THP (Thermal Protection) output THP -0.4 to +7 V

11 All Logic input voltages (x=1~4)

INx_[2:0], EN, CLKEN, CLK, CLKB, CLKIF, CKDL[1:0], CC[1:0], TR[1:0], LVDSTM -0.4 to +7 V

12 Operating junction temperature T Jop -20 to +150 oC

13 Operating free-air Temperature T A 0 to +75 oC

14 Storage temperature T STG -55 to +150 oC

15 Maximum power dissipation P Dmax 4 W

NOTE: Stresses beyond the absolute maximum rati ngs may cause permanent damage to the product. 2. Operating Supply Voltages, Logic Inputs, and Power sequencing

2.1 Operating Supply Voltages

Table 2 Operating Supply Voltages No Items Symbol Min Typ Max Units Condition

1 Logic supply voltage V LL

2.4 2.5 to 3.3 3.6 V Clock mode 1.7 1.8 to 5 V DD V Transparent mode 2 Positive supply voltage V DD 4.75 5 5.25 V 3 Negative supply voltage V SS -5.25 -5 -4.75 V

4 Positive high-voltage supplies V PP1, VPP2 0 - 100 V

5 Negative high-voltage supplies V NN1, VNN2 -100 - 0 V

6 Positive high-voltage difference (V PP1-VPP2) -100 - 100 V

7 Negative high-voltage difference (V NN1-VNN2) -100 - 100 V

8 IC substrate voltage * V SUB - 0 - V

9 V PPx, VNNx slew rate (x=1,2) SR MAX - - 25 V/ms

NOTE: * The package exposed pad internally connected to the IC substrate must be soldered to the ground.

QUAD ±100V 2A TRUE 5-LEVEL ULTRASOUND PULSER Rev.2.2_00 HDL6M05543

2.2 Logic Inputs

Clock (CLK) mode synchronizes data inputs INx_[2:0] (x=1~4 ) with a differential LVDS/CMO S clock. Transparent (TP) mode without using clock is also available. CLK mode: Set CLKEN=0. INx_[2:0] are decoded, clocked, level-translated, then sent to high-voltage output stage. Differential clock input has two modes as shown below.  LVDS CLK mode: set CLKIF=0. See Table 3 and 4 for the logic inputs, CLK, and CLKB.  CMOS CLK mode: set CLKIF=1. See Table 3 for all the logic inputs. TP mode: Set CLKEN=CLKIF=1, CLK=CLKB=0. INx_[2:0] are decoded, le vel-translated, then sent to high-voltage output stage. See Table 3 for all the logic inputs. Table 3 Logic Inputs No Items Symbol Min Typ Max Units Condition 1 High-level logic input voltage V IH 0.8V LL - V LL V 2 Low-level logic input voltage V IL 0 - 0.2V LL V

3 Logic input capacitance C IN - 3 - pF

4 Logic input high current *1 I IH -10 - 10 μA

5 Logic input low current *2 I IL -10 - 10 μA

6 Input rise/fall time t r, t f

• - 800 ps CLK≥100MHz CMOS CLK mode 10~90% CLK, CLKB, INx_[2:0] - - 2.0 ns CLK<100MHz

7 Input clock frequency f CLK - - 200 MHz CMOS CLK mode, CLK, CLKB,

fCLK=1/T, D CLK=τ/T, See Fig.3 8 Duty cycle D CLK 40 50 60 % 9 Data Setup time t SU 1.4 - - ns CLK mode, CKDL[1:0]=’00’ INx_[2:0] to CLK/CLKB, See Fig.3 10 Data Hold time t HLD 1.4 - - ns NOTE: *1) TR[1:0], CKDL[1:0 ], and LVDSTM have 50 μA leak at V LL=2.5V due to 50k Ω internal pull-down resistor. *2) EN, CC[1:0], CLKEN, and CLKIF have 50 μA leak at V LL=2.5V due to 50k Ω internal pull-up resistor. Table 4 LVDS Clock Inputs (CLK, CLKB) No Items Symbol Min Typ Max Units Condition 1 High-level input voltage V IH 1.265 - - V VIHCMR(Typ)+VDIFF(Min)/2 2 Low-level input voltage V IL - - 1.135 V VIHCMR(Typ)-VDIFF(Min)/2 3 Differential input voltage range V DIFF(range) 0.13 0.35 0.49 ±V same as CLK,CLKB voltage swing See Fig.2

4 Differential input voltage peak

to peak swing VDIFF(p-p) 0.26 0.7 0.98 V pp |CLK-CLKB| differential peak-to-peak voltage swing, See Fig.2

5 Input voltage common mode

range VIHCMR 0.84 1.2 1.56 V

6 Differential input impedance R IN 85 100 115 Ω LVDSTM=1

7 High-level input current I IH - - 5.8 mA 8 Low-level input current I IL - - 5.8 mA

9 Input rise/fall time t r, t f - - 600 ps 20% to 80% of V DIFF

10 Input clock frequency f CLK - - 200 MHz LVDS CLK mode, CLK, CLKB,

fCLK=1/T, D CLK=τ/T, See Fig.3 11 Duty cycle D CLK 40 50 60 % NOTE: Please refer to table 3 for the logic inputs other than CLK, CLKB in LVDS CLK mode.

QUAD ±100V 2A TRUE 5-LEVEL ULTRASOUND PULSER HDL6M05543 Rev.2.2_00 Differential input voltage range (V DIFF(range)) Differential input voltage peak to peak swing (V DIFF(p-p)) Fig.2 LVDS clock inputs LVDS/CMOS CLK mode (CLKEN=0) TP mode (CLKEN=1) Fig.3 Setup/Hold Time

2.3 Power Supply Sequencing

Embedded low-voltage (LV) power-up/down reset function provides free power supply sequencing. It also provides fail-safe system in abrupt LV power supply drop. When any one of LV power supplies is turned off during operation, all internal circuits will be immediately reset, and both inputs and outputs will be disabled. Once all LV power supplies are restored, both inputs and outpus will be enabled. VDIFF (range) VIH VIHCMR VIL CLK CLKB VDIFF (p-p) +VDIFF (range) -VDIFF (range) CLK-CLKB CLK INx_[2:0] HVOUTx 50%50% 50%(D0) (D1) tSU 50% (D2) tHLD (D0) (D1) (D2) τ T CLKB 50%50% Don't Care CLK, CLKB INx_[2:0] HVOUTx 50% 50% CLK rise edge position 0.5ns 1.0ns 1.5ns

QUAD ±100V 2A TRUE 5-LEVEL ULTRASOUND PULSER Rev.2.2_00 HDL6M05543 3. Typical Appl ication Circuit Fig.4 Typical Application Circuit VNN2 VPP2 VNN1 VPP1 GND GND VFP1 VFP2 bufferbuffer VSS buffer buffer VFN1 VFN2 buffer VDD buffer HVOUT1 <CH1> <CH2> <CH3> <CH4> HVOUT2 HVOUT3 HVOUT4 IN1_0 IN1_1 IN1_2 IN2_0 IN2_1 IN2_2 IN3_0 IN3_1 IN3_2 IN4_0 IN4_1 IN4_2 EN CLKEN CLKB THP Thermal Protection HDL6M05543 VDD VLL GND VSS P1 P2 P4 N1 N2 N4 D-FF 3-to-8 Decoder Logic I/F LVOUT1 LVOUT2 LVOUT3 LVOUT4 CLK CC[1:0] 250Ω GND ASW TRSW 8ΩGND 10Ω CLKIF TXOUT (internal node) TR[1:0] GND 10kΩ CKDL[1:0] 43,44 47,48 45,46 10,17,25,34 35,42,56,64 C29 +5VCLK :+2.5 to +3.3V TP : +1.8 to +5V C30 -5V C31R1 '00' (default) '11' (default) '0/1' (enable/disable) '00' (default) '0/1' (LVDS/CMOS) CLK : +2.5 to +3.3V Logic TP : +1.8 to +5V Logic XDCR To LNA VPP1 VPP120

60 VFP1

52 VFN1

59 VFP2

'0/1' (CLK/TP) VFN3 buffer VFP3 buffer Level Translator '0/1' (open/term) LVDSTM 33 Logic I/F C26

62 V FN3

53 VFN2

50 VFP3

Floating Voltage Regulators 0 to +100V C10C2 C18 C17 0 to -100V C12C4 C11 C20 C19 0 to +100V C14C6 C13 C22 C21 C28 C270 to -100V C16C8 C15 C24 C23 VNN1(<VNN2) VPP1(>VPP2) Note: 1. High-voltage power supply pins, V PPx/VNNx (x=1,2), can draw fast transient currents up to ±2.0A. Therefore, ceramic capacitors of ≥200V 0.1 μF to 1 μF (C1~8) should be connected as close to the pins as possible for bypassing purpose. 2. Ceramic capacitors of ≥16V 10μF (C9~16), ≥16V 100nF (C17~28), and ≥16V 0.1μF to 1μF (C29~31) should also be connected between high-voltage power supply pi ns and corresponding floating voltage pins V FPx/VFNx, and low-voltage power supply pins for bypassing purpose. Connect those as close to the pins as possible. 3. It is also important to minimize the trace length and to have enough trace width of those high voltage and floating voltage lines. 4. The thermal tab on the bottom of the package must be soldered to the GND. 5. Please refer to Mode Control Tables for detailed CC[1:0], TR[1:0], and CKDL[1:0] setting. 6. High-voltage diodes (e.g. BAV23S) between HVOUTx and VPP1/VNN1 (highest voltage) are recommended to clamp excessive voltage overshoot caused by reverberation.

QUAD ±100V 2A TRUE 5-LEVEL ULTRASOUND PULSER HDL6M05543 Rev.2.2_00 4. Electrical Characteristics

4.1 Operating Supply Currents

Table 5 Operating Supply Currents VLL=2.5V, VDD/VSS=+/-5V, TA=25oC, CLK=CLKB=100MHz/0(CLKEN=0/1), TR[1:0]=CKDL[1:0]=’00’, HVOUT load=220pF//200Ω, LVOUT load=47pF//200Ω, unless otherwise specified. No. Items Symbol Spec Units Conditions Min Typ Max

1 V LL current

• 0.0 - mA Quiescent current-1 EN=1(Disable) INx_[2:0]=’000’ Current mode 3 (CC[1:0]=’11’) VPP1/VNN1=+/-100V VPP2/VNN2=+/-100V LVDS CLK - 0.1 - mA CMOS CLK - 0.05 - mA

2 V DD current

• 2.4 - mA LVDS CLK - 2.4 - mA CMOS CLK - 2.4 - mA 3 V SS current I SSQD - 0.62 - mA 4 V PP1 current I PP1QD - 0.04 - mA 5 V NN1 current I NN1QD - 0.04 - mA 6 V PP2 current I PP2QD - 0.04 - mA 7 V NN2 current I NN2QD - 0.04 - mA

8 V LL current

• 0.05 - mA Quiescent current-2 EN=0(Enable) INx_[2:0]=’000’ Current mode 3 (CC[1:0]=’11’) VPP1/VNN1=+/-100V VPP2/VNN2=+/-100V LVDS CLK - 0.15 - mA CMOS CLK - 0.1 - mA

9 V DD current

• 3 - mA LVDS CLK - 15 - mA CMOS CLK - 13 - mA 10 V SS current I SSQE - 0.9 - mA 11 V PP1 current I PP1QE - 0.16 - mA 12 V NN1 current I NN1QE - 0.16 - mA 13 V PP2 current I PP2QE - 0.16 - mA 14 V NN2 current I NN2QE - 0.16 - mA

15 V LL current

• 0.05 - mA PW operating current EN=0 Current mode 3 (CC[1:0]=’11’) 4-channel active Bipolar 3-level 2-cycle P1/N1-drive f=5MHz, PRT=200 μs V PP1/VNN1=+/-60V VPP2/VNN2=+/-60V LVDS CLK - 0.15 - mA CMOS CLK - 0.1 - mA

16 V DD current

• 6.5 - mA LVDS CLK - 22 - mA CMOS CLK - 20 - mA 17 V SS current I SSPW - 5.5 - mA 18 V PP1 current I PP1PW - 2.2 - mA 19 V NN1 current I NN1PW - 2.4 - mA 20 V PP2 current I PP2PW - 0.16 - mA 21 V NN2 current I NN2PW - 0.16 - mA

QUAD ±100V 2A TRUE 5-LEVEL ULTRASOUND PULSER Rev.2.2_00 HDL6M05543 Table 5 Operating Supply Currents (continued) No. Items Symbol Spec Units Conditions Min Typ Max

22 V LL current

• 0.18 - mA CW operating current-1 EN=0 Current mode 3 (CC[1:0]=’11’) 4-channel active Bipolar 3-level Continuous P2/N2-drive f=5MHz V PP1/VNN1=+/-5V VPP2/VNN2=+/-5V LVDS CLK - 0.26 - mA CMOS CLK - 0.21 - mA

23 V DD current

• 20 - mA LVDS CLK - 35 - mA CMOS CLK - 33 - mA

24 V SS current I SSCW3 - 15 - mA

25 V PP1 current I PP1CW3 - 0.16 - mA 26 V NN1 current I NN1CW3 - 0.16 - mA

27 V PP2 current I PP2CW3 - 84 - mA

28 V NN2 current I NN2CW3 - 86 - mA

29 V LL current

• 0.27 - mA CW operating current-2 EN=0 Current mode 2 (CC[1:0]=’10’) 4-channel active Bipolar 3-level Continuous P2/N2-drive f=5MHz V PP1/VNN1=+/-5V VPP2/VNN2=+/-5V LVDS CLK - 0.3 - mA CMOS CLK - 0.26 - mA

30 V DD current

• 19 - mA LVDS CLK - 35 - mA CMOS CLK - 33 - mA

31 V SS current I SSCW2 - 13 - mA

32 V PP1 current I PP1CW2 - 0.16 - mA 33 V NN1 current I NN1CW2 - 0.16 - mA

34 V PP2 current I PP2CW2 - 80 - mA

35 V NN2 current I NN2CW2 - 83 - mA

36 V LL current

• 0.22 - mA CW operating current-3 EN=0 Current mode 1 (CC[1:0]=’01’) 4-channel active Bipolar 3-level Continuous P2/N2-drive f=5MHz V PP1/VNN1=+/-5V VPP2/VNN2=+/-5V LVDS CLK - 0.30 - mA CMOS CLK - 0.26 - mA

37 V DD current

• 15 - mA LVDS CLK - 31 - mA CMOS CLK - 29 - mA

38 V SS current I SSCW1 - 10 - mA

39 V PP1 current I PP1CW1 - 0.16 - mA 40 V NN1 current I NN1CW1 - 0.16 - mA

41 V PP2 current I PP2CW1 - 77 - mA

42 V NN2 current I NN2CW1 - 80 - mA

43 V LL current

• 0.31 - mA CW operating current-4 EN=0 Current mode 0 (CC[1:0]=’00’) 4-channel active Bipolar 3-level Continuous P2/N2-drive f=5MHz V PP1/VNN1=+/-5V VPP2/VNN2=+/-5V LVDS CLK - 0.35 - mA CMOS CLK - 0.31 - mA

44 V DD current

• 12 - mA LVDS CLK - 28 - mA CMOS CLK - 26 - mA 45 V SS current I SSCW0 - 7.9 - mA 46 V PP1 current I PP1CW0 - 0.16 - mA 47 V NN1 current I NN1CW0 - 0.16 - mA

48 V PP2 current I PP2CW0 - 67 - mA

49 V NN2 current I NN2CW0 - 70 - mA

QUAD ±100V 2A TRUE 5-LEVEL ULTRASOUND PULSER HDL6M05543 Rev.2.2_00

4.2 Static Characteristics

Table 6 Static Characteristics VLL=2.5V, V DD/VSS=+/-5V, T A=25oC, unless otherwise specified. No. Items Symbol Spec Units Conditions Min Typ Max

1 HVOUTx output voltage range HV OUTx -100 - +100 V

2 HVOUTx high-side peak current I OH

• 2.0 - A P1 active, V PP1/VNN1=VPP2/VNN2=+/-60V - 2.0 - A P2 active, V PP1/VNN1=VPP2/VNN2=+/-60V Current mode 3 (CC[1:0]=’11’) - 1.5 - A P2 active, V PP1/VNN1=VPP2/VNN2=+/-60V Current mode 2 (CC[1:0]=’10’) - 1.0 - A P2 active, V PP1/VNN1=VPP2/VNN2=+/-60V Current mode 1 (CC[1:0]=’01’) - 0.5 - A P2 active, V PP1/VNN1=VPP2/VNN2=+/-60V Current mode 0 (CC[1:0]=’00’) - 1.0 - A N3 active, V PP1/VNN1=+/-80V, VPP2/VNN2=+/-20V, Current mode 3

3 HVOUTx high-side GND clamp

peak current IOHCL - 2.0 - A N4 active, V PP1/VNN1=VPP2/VNN2=+/-60V

4 HVOUTx low-side peak current I OL

• 2.0 - A N1 active, V PP1/VNN1=VPP2/VNN2=+/-60V - 2.0 - A N2 active, V PP1/VNN1=VPP2/VNN2=+/-60V Current mode 3 (CC[1:0]=’11’) - 1.5 - A N2 active, V PP1/VNN1=VPP2/VNN2=+/-60V Current mode 2 (CC[1:0]=’10’) - 1.0 - A N2 active, V PP1/VNN1=VPP2/VNN2=+/-60V Current mode 1 (CC[1:0]=’01’) - 0.5 - A N2 active, V PP1/VNN1=VPP2/VNN2=+/-60V Current mode 0 (CC[1:0]=’00’) - 1.0 - A P3 active, V PP1/VNN1=+/-80V, VPP2/VNN2=+/-20V, Current mode 3

5 HVOUTx low-side GND clamp

peak current IOLCL - 2.0 - A P4 active, V PP1/VNN1=VPP2/VNN2=+/-60V

6 HVOUTx high-side on-resistance R ONH

• 11 - Ω P1 active, I OH=100mA - 11 - Ω P2/N3 active, I OH=100mA Current mode 3 (CC[1:0]=’11’) - 13 - Ω P2 active, I OH=100mA Current mode 2 (CC[1:0]=’10’) - 19 - Ω P2 active, I OH=100mA Current mode 1 (CC[1:0]=’01’) - 32 - Ω P2 active, I OH=100mA Current mode 0 (CC[1:0]=’00’)

7 HVOUTx high-side GND clamp

on-resistance RONHCL - 10 - Ω N4 active, I OHCL=100mA

8 HVOUTx low-side on-resistance R ONL

• 10 - Ω N1 active, I OL=100mA - 10 - Ω N2/P3 active, I OL=100mA Current mode 3 (CC[1:0]=’11’) - 12 - Ω N2 active, I OL=100mA Current mode 2 (CC[1:0]=’10’) - 18 - Ω N2 active, I OL=100mA Current mode 1 (CC[1:0]=’01’) - 30 - Ω N2 active, I OL=100mA Current mode 0 (CC[1:0]=’00’)

9 HVOUTx low-side GND clamp

on-resistance RONLCL - 11 - Ω P4 active, I OLCL=100mA

10 HVOUTx off-capacitance C HVOFF - 40 - pF TXOUTx=HiZ, TRSW=off

QUAD ±100V 2A TRUE 5-LEVEL ULTRASOUND PULSER Rev.2.2_00 HDL6M05543

4.3 Dynamic Characteristics

Table 7 Dynamic Characteristics VLL=2.5V, V DD/VSS=+/-5V, VPP1/VNN1=VPP2/VNN2=+/-60V, T A=25oC, TR[1:0]=CKDL[1:0 ]=’00’, CC[1:0]=’11’, CLK=CLKB=100MHz/0(CLKEN=0/1), HV OUT load=220pF//200 Ω, LV OUT load=47pF//200 Ω, unless otherwise specified. No. Items Symbol Spec Units Conditions Min Typ Max

1 Output frequency f OUT - 20 - MHz

2 Output rise

• 31 - ns See Fig.5 CLK mode - 39 - ns

3 Output fall

• 31 - ns CLK mode - 39 - ns

4 Output rise

• 31 - ns CLK mode - 39 - ns

5 Output fall

• 31 - ns CLK mode - 39 - ns

6 Propagation delay matching Δtd - ±1 ±3 ns

7 Output rise time

• 16 - ns P1 active See Fig.5 - 16 - ns P2 active, CC[1:0]=’11’ - 19 - ns P2 active, CC[1:0]=’10’ - 27 - ns P2 active, CC[1:0]=’01’ - 52 - ns P2 active, CC[1:0]=’00’ trCL - 10 - ns P4 active

8 Output fall time

• 16 - ns N1 active - 16 - ns N2 active, CC[1:0]=’11’ - 19 - ns N2 active, CC[1:0]=’10’ - 27 - ns N2 active, CC[1:0]=’01’ - 52 - ns N2 active, CC[1:0]=’00’ tfCL - 10 - ns N4 active 9 2 nd harmonic distortion HD2 - -40 - dBc Bipolar, 2-cyc, f OUT=5MHz See Fig.6

10 Pulse cancellation

11 RMS output jitter t J - 10 - ps Bipolar CW, f OUT=5MHz

VPP1/VNN1=VPP2/VNN2=+/-5V

12 Crosstalk between channels X TLK - -70 - dB fOUT=5MHz, 10V p-p,

HVOUT load=50 Ω

13 Output enable time

• 28 - ns See Fig.7 LVDS CLK - 600 - ns CMOS CLK - 600 - ns

14 Output disable time t DS - 36 - ns

15 Clock mode enable time t CLKEN - 600 - ns

16 Clock mode disable time t CLKDS - 36 - ns

QUAD ±100V 2A TRUE 5-LEVEL ULTRASOUND PULSER HDL6M05543 Rev.2.2_00

4.4 Integrated Peripheral Circuits Characteristics

Table 8 T/R Switch Characteristics VLL=2.5V, V DD/VSS=+/-5V, VPP1/VNN1=VPP2/VNN2=+/-60V, T A=25oC, unless otherwise specified. No. Items Symbol Spec Units Conditions Min Typ Max 1 LVOUTx output voltage range LV OUTx -0.85 - +0.85 V

2 TRSW on-resistance R ONTR - 10 - Ω HVOUTx=100mV, LV OUTx=0V

3 TRSW on-capacitance C ONTR - 15 - pF

4 TRSW off-resistance on HVOUTx R OFFTRHV 1 - - M Ω

5 TRSW off-resistance on LVOUTx R OFFTRLV 8 10 12 k Ω

6 Spike voltage

on HV OUTx and LV OUTx VTRN - - 50 mVPP 50pF//200Ω load on HV OUTx 20pF//200Ω load on LV OUTx

7 TRSW turn-on time

TR[1:0]=’00’ tdTRON - 400 - ns Logic input-to-ready for Rx signal See Fig.8 TR[1:0]=’01’ - 500 - ns 8 TRSW turn-off time t dTROFF - 50 100 ns See Fig.8

9 Tx setup time t TXSU 100 - - ns INx_[2:0]=’100’(GND) for at least

100ns before Tx burst. See Fig.8 Analog Switch Table 9 Analog Switch Characteristics TA=25oC No. Items Symbol Spec Units Conditions Min Typ Max

1 ASW on-resistance RONASW - 250 - Ω

Table 10 Output HV Blocking Diode Characteristics TA=25oC No. Items Symbol Spec Units Conditions Min Typ Max

1 Forward voltage V FHVD

• 1.0 - V IF=100mA - 1.2 - V IF=200mA

2 Reverse voltage V RHVD 200 - - V IR=1μA

Table 11 Output LV Noise-cut Diode Characteristics TA=25oC No. Items Symbol Spec Units Conditions Min Typ Max

1 Forward voltage V FLVD

• 1.1 - V IF=100mA - 1.25 - V IF=200mA

QUAD ±100V 2A TRUE 5-LEVEL ULTRASOUND PULSER Rev.2.2_00 HDL6M05543 Thermal Protection Table 12 Thermal Protection Characteristics VLL=2.5V, V DD/VSS=+/-5V, T A=25oC, unless otherwise specified. No. Items Symbol Spec Units Conditions Min Typ Max 1 THP pull-up voltage V PUTHP - - 5.25 V Open drain 2 THP output current I THP - 1.0 - mA - 3 THP output low voltage V OLTHP - - 0.5 V THP active, V LL=2.5V, I THP=1mA

4 THP temperature threshold T THP 100 110 120 ºC

5 THP reset hysteresis T HYSTHP - 10 - ºC

QUAD ±100V 2A TRUE 5-LEVEL ULTRASOUND PULSER HDL6M05543 Rev.2.2_00 5. Switching Time Diagram Fig.5 Propagation delay and Output rise/fall time Example waveforms: VPP/VNN=+/-60V, f 0=2.5MHz, 2-cycle, HV OUT load=220pF//200 Ω Fig.6 2 nd harmonic distortion and Pulse cancellation INx_2 VLL GND INx_1 VLL GND INx_0 VLL GND HVOUTx VPP1 GND VNN1 50% 50% 90% 10% tdf 10% 50% tf 10% 50% 90% tr tdr 50% 10% tdfCL 90% tfCL tdrCL trCL 50% 50% 90% HD2 HDPC2 HDPC 2xf0 V: 10dB/div H: 1.25MHz/div V: 20V/div H: 100ns/div fft(A) fft(A+B) wave A wave B wave A+B

QUAD ±100V 2A TRUE 5-LEVEL ULTRASOUND PULSER Rev.2.2_00 HDL6M05543 Fig.7 Output enable/disable and Clock enable/disable time Fig.8 T/R Switch turn-on/off time VPP1 HVOUTx 50% INx_[2:0] EN VLL GND '011' (VPP1) GND 50% DisableDisableMode Enable tEN=td 10% 10% tDS=td TP CLK VLL GND DATA VLL GND HVOUTx 50% 50% TPMode CLKEN VLL GND CLK (D0) (D1) (D0) (D1) tCLKEN 50% (D2) tCLKDS (D2) setup tsetup 1/fCLK td setup tsetup td Output enable/disable time Clock enable/disable time HVOUTx Tx/Rx mode Rx Tx setup Tx Rx setup Rx LVOUTx GND V PP1V NN1G N DTXOUTx (internal node) ONS1 ON OFF ON OFF ON OFFOFFTRSW TR[1:0]=0~300ns tdTRON ON ON OFF tdTROFF ON tTXSU

QUAD ±100V 2A TRUE 5-LEVEL ULTRASOUND PULSER HDL6M05543 Rev.2.2_00 6. Truth Table and Mode Control tables Table 13 Truth table Note: V PP1/ V NN1=+/-HV1, V PP2/ V NN2=+/-HV2, x=1~4 Note: When the current mode is other than 3 (CC[1:0] ≠'11'), both P3 and N3 are always in off-state. Table 14 P2/N2 drive current mode Note: Recommended mode is as follows:  Current mode 2 or 3 for high amplitude short cycle pulse waveforms, or for driving heavy load  Current mode 0 or 1 for low amplitude long pulse trai n waveforms (e.g. CW), or for driving light load Table 15 TRSW S1-S2 turn-on overlap time control mode Note: Detailed switching time diagram is shown in Fig.8. Table 16 Clock edge timing control mode Note: Detailed switching time diagram is shown in Fig.3. Logic Inputs Internal MOSFET state Output state E N I N x _ 2 I N x _ 1 I N x _ 0 P 1N 1P 2N 2P 3N 3P 4N 4 A S W T R S W T X OUTxL V OUTx +HV1 -HV1 +HV2 -HV2 -HV2 +HV2 GND GND GND S1 S2 S3 (internal node) 0 0 0 0 OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON OFF HiZ 10k Ω

0001 O F F O F F ON OFF OFF ON * OFF OFF OFF OFF ON OFF +HV2 10k Ω

0 0 1 0 OFF OFF OFF OFF OFF OFF OFF OFF OFF ON OFF ON HiZ HV OUTx

0011 ON O F FO F FO F FO F FO F FO F FO F FO F FO F F ON OFF +HV1 10k Ω

0 1 0 0 OFF OFF OFF OFF OFF OFF ON ON ON OFF ON OFF GND 10k Ω 0 1 0 1 OFF OFF OFF ON ON * O F FO F FO F FO F FO F F ON OFF -HV2 10k Ω 0 1 1 0 OFF OFF OFF OFF OFF OFF ON ON ON ON OFF ON GND HV OUTx

0111 O F F ON OFF OFF OFF OFF OFF OFF OFF OFF ON OFF -HV1 10k Ω

1 X X X OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON OFF HiZ 10k Ω

Iout [A] Current Mode CC1 CC0 P2 N2 00 0 0 . 5 0 . 5 10 1 1 1 21 0 1 . 5 1 . 5 31 1 2 2 S1-S2 ON TRSW Control Mode TR1 TR0 overlap time [ns] 0 0 0 0 (default) 10 1 1 0 0 21 0 2 0 0 31 1 3 0 0 CLK CLK Edge Control Mode CKDL1 CKDL0 edge [ns] 0 0 0 0 (default) 10 1 0 . 5 21 0 1 31 1 1 . 5

QUAD ±100V 2A TRUE 5-LEVEL ULTRASOUND PULSER Rev.2.2_00 HDL6M05543 7. Pin Configuration Table 17 Pin Configuration Pin# Pin Name I/O Function

1 IN1_0 I The least significant bit of logic input of channel 1

2 IN1_1 I The 2nd significant bit of logic input of channel 1

3 IN1_2 I The most significant bit of logic input of channel 1

4 IN2_0 I The least significant bit of logic input of channel 2

5 IN2_1 I The 2nd significant bit of logic input of channel 2

6 IN2_2 I The most significant bit of logic input of channel 2

7 VDD - Positive low voltage power supply (+5V)

8 CLK I Positive clock input (up to 200MHz)

9 CLKB I Negative clock Input (up to 200MHz)

10 GND - Drive power ground (0V)

11 IN3_0 I The least significant bit of logic input of channel 3

12 IN3_1 I The 2nd significant bit of logic input of channel 3

13 IN3_2 I The most significant bit of logic input of channel 3

14 IN4_0 I The least significant bit of logic input of channel 4

15 IN4_1 I The 2nd significant bit of logic input of channel 4

16 IN4_2 I The most significant bit of logic input of channel 4

17 GND - Drive power ground (0V)

18 LVOUT4 O Low voltage output of channel 4

19 VFN3 - Built-in power supply for N-MOS (N3) gate drive

20 VPP1 - Positive high voltage power supply 1 (0 to +100V)

21 VFP1 - Built-in power supply for P-MOS (P1) gate drive

22 VFP2 - Built-in power supply for P-MOS (P2) gate drive

23 VPP2 - Positive high voltage power supply 2 (0 to +100V)

24 HVOUT4 O High voltage output of channel 4

25 GND - Drive power ground (0V)

26 HVOUT3 O High voltage output of channel 3

27 VNN2 - Negative high voltage power supply 2 (0 to -100V)

28 VFN2 - Built-in power supply for N-MOS (N2) gate drive

29 VFN1 - Built-in power supply for N-MOS (N1) gate drive

30 VNN1 - Negative high voltage power supply 1 (0 to -100V)

31 VFP3 - Built-in power supply for P-MOS (P3) gate drive

32 LVOUT3 O Low voltage output of channel 3

QUAD ±100V 2A TRUE 5-LEVEL ULTRASOUND PULSER HDL6M05543 Rev.2.2_00 Table 17 Pin Configuration (cont.) Pin# Pin Name I/O Function

33 LVDSTM - Control of LVDS termination between CLK and CLKB, Hi=embedded 100 Ω, Low=open

(50kΩ internal pull-down resistor)

34 GND - Drive power ground (0V)

35 GND - Drive power ground (0V)

36 CLKIF I Control of clock interface, Hi=differential CMOS, Low=LVDS (50k Ω internal pull-up resistor)

37 CLKEN I Control of clock enable, Hi=clock disable, Low=clock enable (50k Ω internal pull-up resistor)

38 EN I Control of drive output enable, Hi=off, Low=on (50k Ω internal pull-up resistor)

39 V SS - Negative low voltage power supply (-5V)

40 V LL - Positive voltage supply of logi c input interface (1.8 to 5V)

41 THP O Thermal protection output flag, open N-MOS drain

42 GND - Drive power ground (0V)

43 TR0 I Lower bit of control of T/R switch S1 and S2 turn-on overlap time

(50kΩ internal pull-down resistor)

44 TR1 I Upper bit of control of T/R switch S1 and S2 turn-on overlap time

(50kΩ internal pull-down resistor)

45 CKDL0 I Lower bit of control of clock edge timing (50k Ω internal pull-down resistor)

46 CKDL1 I Upper bit of control of clock edge timing (50k Ω internal pull-down resistor)

47 CC0 I Lower bit of control of P2/N2 drive current (50k Ω internal pull-up resistor)

48 CC1 I Upper bit of control of P2/N2 drive current (50k Ω internal pull-up resistor)

49 LV OUT2 O Low voltage output of channel 2

50 V FP3 - Built-in power supply for P-MOS (P3) gate drive

51 V NN1 - Negative high voltage power supply 1 (0 to -100V)

52 V FN1 - Built-in power supply for N-MOS (N1) gate drive

53 V FN2 - Built-in power supply for N-MOS (N2) gate drive

54 V NN2 - Negative high voltage power supply 2 (0 to -100V)

55 HV OUT2 O High voltage output of channel 2

56 GND - Drive power ground (0V)

57 HV OUT1 O High voltage output of channel 1

58 V PP2 - Positive high voltage power supply 2 (0 to +100V)

59 V FP2 - Built-in power supply for P-MOS (P2) gate drive

60 V FP1 - Built-in power supply for P-MOS (P1) gate drive

61 V PP1 - Positive high voltage power supply 1 (0 to +100V)

62 V FN3 - Built-in power supply for N-MOS (N3) gate drive

63 LV OUT1 O Low voltage output of channel 1

64 GND - Drive power ground (0V)

QUAD ±100V 2A TRUE 5-LEVEL ULTRASOUND PULSER Rev.2.2_00 HDL6M05543  Package Table 18 Package Drawing Codes Package Name Dimension Tray Marking Land Packing QFN-64(0909)B QN064-B-P-SD QFN9x9-B-T-S D QN064-B-M-S2 QN064-B-L-SD QN064-B-K-SD  Storage, Mounting 1. Storage conditions 1. 1 The storage location should be kept at 5 to 35 °C and 40 to 70% relative humidity. Keeping in a dry box is recommended. Moisture-proof property is assured fo r 12 months from delivery date for sealed moisture- proof packing, while it is guaranteed for 7 days from unpacked date under the condition above. 1. 2 When the storage conditions do not c onform to those above or other cond itions occur indicating moisture exposure, the ICs should be dried to avoid package cracks. A baking process at 125°C lasting for 24 hours results in sufficient dehumidification. The baking is not allowed more than t wice, and the ICs should be mounted within 7 days after initial baking or wit hin 10 days of total exposure after the second dehumidification. 2. Reflow soldering The temperature rise may be different in the resin and a terminal part due to the reflow soldering. It is necessary to check the package surface temperature (resin) before setting the temperature profile. Fig. 9 shows the resistance to soldering heat condition for package (Reflow method). Confirm the heat resistance of the package shown below. (Based on JEDEC J-STD-020). More than 217°C 60 to 150 s Time: 8 min max. to peak Ramp up rate: 3°C/s max. 10 s max. Peak temperature: 260°C More than 255°C 30 s max. Temperature measurement point: resin surface temperature Temp. Time 25°C Ramp down rate: 6°C/s max. 200°C 150°C Preheat area: 60 to 120 s Fig.9 Resistance to Soldering Heat Condition for Package (Reflow Method)

QUAD ±100V 2A TRUE 5-LEVEL ULTRASOUND PULSER HDL6M05543 Rev.2.2_00  Important Notice 1. ABLIC Inc. warrants performance of it s hardware products (hereinafter calle d “products”) to the specifications applicable at the time of sale in accordance with the Product Specificati on. Testing and other quality control techniques are utilized to the ext ent ABLIC Inc. needs to meet specif ications described in the Product Specification. Specific te sting of all parameters of each device is not necessarily performed, except those mandated by related laws and/or regulations. 2. Should any claim be made within one month of product de livery about products’ failure to meet performance described in the Product Specification, all the products in relevant lot(s) shall be re-tested and re-delivered. Products delivered more than one month before such claim shall not be counted for such response. 3. ABLIC Inc. assumes no obligation or any way of com pensation should any fault about customer products and applications using ABLIC Inc. products be found in marketpl ace. Only in such a case fault of ABLIC Inc. is evident and products concerned do not meet the Product Specification, compensation shall be conducted if claimed within one year of product delivery up to in the way of product replacement or payment of equivalent amount. 4. ABLIC Inc. reserves the right to make changes to t he Product Specification at any time and to discontinue mass production of the relevant products without notice. Customers are advised bef ore placing orders to confirm that the Product Specification of inquiry is the latest version and that the rele vant product is currently on mass production status. 5. In no event shall ABLIC Inc. be liable for any damage that may result from an accident or any other cause during operation of the user’s units according to the Product Specification. ABLIC Inc. assumes no responsibility for any intellectual property claims or any ot her problems that may result from a pplications of information, products or circuits described in the Product Specification. 6. No license is granted by the Product Specification under any patents or other rights of any third party or ABLIC Inc. 7. The Product Specification may not be r eproduced or duplicated, in any form, in whole or in part, without the expressed written permission of ABLIC Inc. 8. Resale of ABLIC Inc. products with statements differ ent from or beyond the parameters described in the Product Specification voids all express and any implied warra nties for the products, and is an unfair and deceptive business practice. ABLIC Inc. is not responsible or liable for any such statements. 9. Products (technologies) described in the Product Specif ication are not to be provided to any party whose purpose in their application will hinder maintenance of in ternational peace and safety nor are they to be applied to that purpose by their direct purc hasers or any third party. When exporti ng those products (technologies), the necessary procedures are to be taken in accordance with related laws and regulations.

QUAD ±100V 2A TRUE 5-LEVEL ULTRASOUND PULSER Rev.2.2_00 HDL6M05543  Cautions 1. Customers are advised to follow the cautions below to protect products from damage ca used by electrical static discharge (ESD). 1. 1 Material of container or any device to carry pr oducts should be free from ESD, which may be caused by vibration while transportation. It is recommended that electric-conductive container or aluminum sheet be used as an effective countermeasure. 1. 2 Those that touch products, such as work platform, machine, or measuremen t/test equipment, should be grounded. 1. 3 Those who deal with products should be grounded through a large series impedance around 100k Ω to 1MΩ. 1. 4 Prevent friction with other materials made with high polymer. 1. 5 Prevent vibration or friction when carrying the printed circuit board (P CB) where products are mounted. To short circuit terminals is a recommended countermeasure to keep the same electric potential on the PCB. 1. 6 Avoid dealing with or storing produc ts in an extremely arid environment. 2. “Absolute maximum ratings” should never be exceeded during use regardless of any change in external conditions. Otherwise, products may be damaged or destroyed. In no event shall ABLIC Inc. be liable for any failure in products or any secondary damage resulting from use at a value exceeding the absolute maximum ratings. 3. Products may experience failures due to accident or u nexpected surge voltages. Accordingly, adopt safe design features, such as redundancy or prev ention of erroneous action, to avoi d extensive damage in the event of a failure. (If a semiconductor device fails, there may be cases in which the semiconductor device, wiring or wiring pattern will emit smoke or cause a fire or in which the semiconductor device will burst.) 4. Products may experience failures or malf unction in poor surroundings, such as electrical leakage in products due to long-term use in high humidity, malfunctioning or pe rmanent damage due to chemical reaction of products in corrosive environment or due to discharge by strongly charged object near products or due to excessive mechanical shock. To use products in radiation environment is not assumed. To use products near material easy to ignite may cause a fire due to its flammable package. Avoid using products in such environment or take appropriate countermeasures depending on the environment. 5. Products are not designed, manufactured, or warranted to be suitable for use where extremely high reliability is required (such as use in nuclear pow er control, aerospace and aviation, traffic equipment, life-support-related medical equipment, fuel control equipment and various kinds of safety equipment). Inclusion of products in such application shall be fully at the risk of customers. ABLIC Inc. assumes no liability for applications assistance, customer product design, or performance.

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Disclaimers (Handling Precautions) 1. All the information described herein (product data, specific ations, figures, tables, programs, algorithms and application circuit examples, et c.) is current as of publishing date of this document and is subject to change without notice. 2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. ABLIC Inc. is not liable for any losses, damages, claims or dem ands caused by the reasons other than the products described herein (hereinafter "the products") or infringement o f third-party intellectual property right and any other right due to the use of the information described herein. 3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described herein. 4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute maximum ratings, operation voltage range and electrical characteristics, etc. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to the use of the products outside their specified ranges. 5. Before using the products, co nfirm their applications, and the laws and regulations of the region or country where they are used and verify suitability, safety and other factors for the intended use. 6. When exporting the products, comply with the Foreign Exchang e and Foreign Trade Act and all other export-related laws, and follow the required procedures. 7. The products are strictly prohibited from using, providing o r exporting for the purposes of the development of weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by any provision or export to the person or entity who i ntends to develop, manufacture, use or store nuclear, biological or chemical weapons or missiles, or use any other military purposes. 8. The products are not designed to be used as part of any devi ce or equipment that may affect the human body, human life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment, aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by ABLIC, Inc. Do not apply the products to the above listed devices and equipments. ABLIC Inc. is not liable for any losses, damages, claims or dem ands caused by unauthorized or unspecified use of the products. 9. In general, semiconductor products may fail or malfunction w ith some probability. The user of the products should therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread prevention measures, and malfunction prevention to prevent acci dents causing injury or death, fires and social damage, etc. that may ensue from the products' failure or malfunction. The entire system in which the products are used must be sufficiently evaluated and judged whether the products are allowed to apply for the system on customer's own responsibility. 10. The products are not designed to be radiation-proof. The ne cessary radiation measures should be taken in the product design by the customer depending on the intended use. 11. The products do not affect human health under normal use. H owever, they contain chemical substances and heavy metals and should therefore not be put in the mouth. The fractu re surfaces of wafers and chips may be sharp. Be careful when handling these with the bare hands to prevent injuries, etc. 12. When disposing of t he products, comply with the laws and ordinances of the country or region where they are used. 13. The information described herein contains copyright informa tion and know-how of ABL IC Inc. The information described herein does not convey any license under any intellec tual property rights or any other rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the inf ormation from this document or any part of this document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express permission of ABLIC Inc. 14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales representative. 15. This Disclaimers have been delivered in a text using the Ja panese language, which text, despite any translations into the English language and the Chinese language, shall be controlling. 2.4-2019.07 www.ablic.com