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S-24CS01A/02A/04A H Series www.ablicinc.com FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM © ABLIC Inc., 2009-2018 Rev.3.1_03 The S-24CS01A/02A/04A H series is a hi gh temperature operation 2-wire serial E 2PROM for automotive components. The S-24CS01A/02A/04A H series has the capacity of 1 K-bit, 2 K-bit and 4 K-bit, and the organization is 128 words × 8 bits, 256 words × 8 bits and 512 words × 8 bits. Page write and sequential read are available. Caution Before using the product in automobile control unit or medical equipment, contact to ABLIC Inc. is indispensable. Features
- Operating voltage range: Read 2.55 V to 5.5 V (Ta = − 40°C to +105°C) Write 2.55 V to 5.5 V (Ta = − 40°C to +105°C)
- Page write: 8 bytes / page (S-24CS01A/02A) 16 bytes / page (S-24CS04A)
- Sequential read
- Operating Frequency: 400 kHz (VCC = 2.55 V to 5.5 V, Ta = −40°C to +85°C) 350 kHz (VCC = 2.55 V to 5.5 V, Ta = +85°C to +105°C)
- Write time: 10.0 ms max.
- Write protect function during the low power supply voltage
- Endurance: 106 cycles/word*1 (Ta = +85°C) 5 × 105 cycles/word*1 (Ta = +105°C)
- Data retention: 100 years (Ta = +25°C) 20 years (Ta = +105°C)
- Memory capacity: S-24CS01A 1 Kbit S-24CS02A 2 Kbit S-24CS04A 4 Kbit
- Write protect: 100%
- Initial delivery state: FFh
- Operation temperature range: Ta = −40°C to +105°C
- Lead-free (Sn 100%), halogen-free *1. For each address (Word: 8-bit) Packages
- 8-Pin SOP(JEDEC)
- 8-Pin TSSOP
- TMSOP-8 www.ablic.com
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM S-24CS01A/02A/04A H Series Rev.3.1_03 Pin Configurations 1. 8-Pin SOP (JEDEC) Table 1 Top view Figure 1 S-24CS01AFJ-TBH-U S-24CS02AFJ-TBH-U S-24CS04AFJ-TBH-U Pin No. Symbol Description
1 A0 Address input (No connection in S-24CS04A*1)
2 A1 Address input
3 A2 Address input
4 GND Ground
5 SDA Serial data input / output
6 SCL Serial clock input
Connected to V CC: Protection valid Connected to GND: Protection invalid
8 VCC Power supply
- 8-Pin TSSOP Table 2 Top view Figure 2 S-24CS01AFT-TBH-U S-24CS02AFT-TBH-U S-24CS04AFT-TBH-U Pin No. Symbol Description
Connected to V CC: Protection valid Connected to GND: Protection invalid
- TMSOP-8 Table 3 Top view Figure 3 S-24CS01AFM-TFH-U S-24CS02AFM-TFH-U S-24CS04AFM-TFH-U Pin No. Symbol Description
Connected to V CC: Protection valid Connected to GND: Protection invalid *1. Connect to the GND pin or VCC. Remark Refer to the "Package Drawings" for the details.
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM Rev.3.1_03 S-24CS01A/02A/04A H Series Block diagram VCC GND Serial Clock Controller Device Address Comparator Address Counter Y Decoder Data Output ACK Output Controller Start / Stop Detector Data Register E2PROM X Decoder Selector High-Voltage Generator SCL SDA DIN DOUT R / W LOAD INC COMP LOAD WP A0*1 Voltage Detector *1. This pin is not available for S-24CS04A. Figure 4
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM S-24CS01A/02A/04A H Series Rev.3.1_03 Absolute Maximum Ratings Table 4 Item Symbol Absolute Maximum Ratings Unit Power supply voltage V CC −0.3 to +7.0 V Input voltage V IN −0.3 to +7.0 V Output voltage V OUT −0.3 to +7.0 V Operating ambient temperature T opr −40 to +105 °C Storage temperature T stg −65 to +150 °C Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Recommended Operating Conditions Table 5 Item Symbol Conditions −40°C to +85°C +85°C to +105°C UnitMin. Max. Min. Max. Power supply voltage V CC Read Operation 1. 8 5.5 2.55 5.5 V Write Operation 2. 55 5.5 2.55 5.5 V High level input voltage V IH VCC = 4.5 V to 5.5 V 0.7 ×VCC VCC 0.7×VCC VCC V VCC = 2.55 V to 4.5 V 0.7 ×VCC VCC 0.7×VCC VCC V VCC = 1.8 V to 2.55 V 0.8 ×VCC V CC ⎯ ⎯ V Low level input voltage V IL VCC = 1.8 V to 2.55 V 0.0 0.2 ×VCC ⎯ ⎯ V Pin Capacitance Table 6 (Ta = 25°C, f = 1.0 MHz, VCC = 5 V) Item Symbol Conditions Min. Max. Unit Input capacitance C IN VIN = 0 V (S-24CS01A/02A: SCL, A0, A1, A2, WP) ⎯ 10 pF VIN = 0 V (S-24CS04A: SCL, A1, A2, WP) ⎯ 10 pF Input/output capacitance C I / O VI / O = 0 V (SDA) ⎯ 10 pF Endurance Table 7 Item Symbol Operating ambient temperature Min. Max. Unit Endurance N W −40°C to +85°C 10 6 ⎯ cycles / word*1 +85°C to +105°C 5 ×105 ⎯ cycles / word*1 *1. For each address (Word: 8 bits) Data Retention Table 8 Item Symbol Operating ambient temperature Min. Max. Unit Data retention ⎯ +25°C 100 ⎯ year −40°C to +105°C 20 ⎯ year
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM Rev.3.1_03 S-24CS01A/02A/04A H Series DC Electrical Characteristics Table 9 (1/2) Item Symbol Conditions −40°C to +85°C UnitVCC = 4.5 V to 5.5 V f = 400 kHz VCC = 2.7 V to 4.5 V*1 f = 100 kHz VCC = 1.8 V to 2.7 V f = 100 kHz Current consumption (READ) I Current consumption (WRITE) ICC2 ⎯ ⎯ 4.0 ⎯ 1.5 ⎯ ⎯ mA *1. VCC = 2.55 V to 4.5 V in Write Table 9 (2/2) Item Symbol Conditions +85°C to +105°C Unit VCC = 2.55 V to 5.5 V f = 350 kHz Min. Max. Current consumption (READ) I CC1 ⎯ ⎯ 0.8 mA Current consumption (WRITE) ICC2 ⎯ ⎯ 4.0 mA Table 10 (1/2) Item Symbol Conditions −40°C to +85°C UnitVCC = 4.5 V to 5.5 V VCC = 2.55 V to 4.5 V VCC = 1.8 V to 2.55 V Standby current consumption I SB V IN = VCC or GND ⎯ 2.0 ⎯ 2.0 ⎯ 2.0 μA Input leakage current I LI V IN = GND to VCC ⎯ 1.0 ⎯ 1.0 ⎯ 1.0 μA Output leakage current I LO V OUT = GND to VCC ⎯ 1.0 ⎯ 1.0 ⎯ 1.0 μA Low level output voltage V OL IOL = 3.2 mA ⎯ 0.4 ⎯ 0.4 ⎯ ⎯ V IOL = 1.5 mA ⎯ 0.3 ⎯ 0.3 ⎯ 0.5 V Table 10 (2/2) Item Symbol Conditions +85°C to +105°C Unit VCC = 2.55 V to 5.5 V Min. Max. Standby current consumption I SB V IN = VCC or GND ⎯ 2.0 μA Input leakage current I LI V IN = GND to VCC ⎯ 1.0 μA Output leakage current I LO V OUT = GND to VCC ⎯ 1.0 μA Low level output voltage V OL IOL = 3.2 mA ⎯ 0.4 V IOL = 1.5 mA ⎯ 0.3 V Current address hold voltage V AH ⎯ 1.5 5.5 V
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM Rev.3.1_03 S-24CS01A/02A/04A H Series Table 13 Item Symbol −40°C to +85°C +85°C to +105°C Unit VCC = 2.55 V to 5.5 V V CC = 2.55 V to 5.5 V Write time t WR — 4.0 10.0 — 4.0 10.0 ms SCL SDA D0 Write data Acknowledge Stop Condition Start Condition tWR Figure 7 Write Cycle Timing
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM S-24CS01A/02A/04A H Series Rev.3.1_03 Pin Functions 1. Address input pins (A0, A1 and A2) The slave address is assigned by connecting pins A0, A1 and A2 to the GND or to the V CC respectively. One of the eight different slave address can be assigned to the S-24CS01A/02A by the combination of pins A0, A1 and A2. The slave address is assigned by connecting pi ns A1 and A2 to the GND or to the V CC respectively. One of the four different slave address can be assigned to the S-24CS04A by the combination of pins A1 and A2. The given slave address, which is com pared with the slave address transmitted fr om the master device, is used to select the one among the multiple devic es connected to the bus. The address input pin should be connected to the GND or to the V CC. 2. SDA (Serial data input / output) pin The SDA pin is used for bi-directional transmission of seri al data. It consists of a signal input pin and an Nch open- drain output pin. The SDA line is usually pulled up to the V CC, and OR-wired with other open-drain or open-collector output devices. 3. SCL (Serial clock input) pin The SCL pin is used for serial clock input. Since signals ar e processed at the rising or falling edge of the SCL clock input signal, attention should be paid to the rising time and falling time to conform to the specifications. 4. WP (write protect input) pin The write protect is enabled by connecting the WP pin to the VCC. When there is no need for write protect, connect the pin to the GND. Initial Delivery State Initial delivery state of all addresses is "FFh".
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM Rev.3.1_03 S-24CS01A/02A/04A H Series Operation 1. Start condition Start is identified by a high to low transition of the SDA line while the SCL line is stable at high. Every operation begins from a start condition. 2. Stop condition Stop is identified by a low to high transition of the SDA line while the SCL line is stable at high. When a device receives a stop condition during a read s equence, the read operation is interrupted, and the device enters standby mode. When a device receives a stop condition duri ng a write sequence, the rec eption of the write data is halted, and the S-24CS01A/02A/04A initiates a write cycle. tSU.STA tHD.STA tSU.STO Start Condition Stop Condition SCL SDA Figure 8 Start / Stop Conditions
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM Rev.3.1_03 S-24CS01A/02A/04A H Series 5. Device addressing To start communication, the master device on the system generat es a start condition to the bus line. Next, the master device sends 7-bit device address and a 1-bit read / write instruction code on to the SDA bus. The 4 most significant bits of the device address are called the "Device Code", and are fixed to "1010". In S-24CS01A/02A, successive 3 bits are called the “Slave Address”. These 3 bits are used to identify a device on the system bus and are compared with the predetermined value wh ich is defined by the address input pins (A0, A1 and A2). When the comparison result matches, the slave device responds with an acknowledge during the 9th clock cycle. In S-24CS04A, successive 2 bits are called the "Slave Addr ess". These 2 bits are used to identify a device on the system bus and are compared with the predetermined value wh ich is defined by the address input pins (A1 and A2). When the comparison result matches, the slave device responds with an acknowledge during the 9th clock cycle. The successive 1 bit (P0) is used to define a page addr ess and choose the two 256-byte memory blocks (Address 000h to 0FFh and 100h to 1FFh). Slave Address 1 0 1 0 A2 A1 A0 R/W Device Code LSB MSB S-24CS01A/02A Slave / Page Address Device Code S-24CS04A 1 0 1 0 A2 A1 P0 R/W MSB LSB Figure 11 Device Address
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM S-24CS01A/02A/04A H Series Rev.3.1_03 6. Write 6. 1 Byte write When the master sends a 7-bit device addr ess and a 1-bit read / write instruction code set to "0", following a start condition, the S-24CS01A/02A/04A acknowledges it. The S-24CS01A/02A/04A then receives an 8-bit word address and responds with an acknowledge. After the S-24CS01A/ 02A/04A receives 8-bit write data and responds with an acknowledge, it receives a stop condition and that initiates the write cycle at the addressed memory. During the write cycle all operations are forbidden and no acknowledge is generated. A2 A1 A0 S T A R T 1 0 1 0 W R I T E DEVICE ADDRESS R W M S B SDA LINE ADR INC (ADDRESS INCREMENT) A C K L S B WORD ADDRESS S T O P DATA W7 W6 W5 W4 W3 W2 W1 W0 D7 D6 D5 D4 D3 D2 D1 D0 A C K A C K Remark 1. A0 is P0 in the S-24CS04A. 2. W7 is optional in the S-24CS01A. Figure 12 Byte Write
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM Rev.3.1_03 S-24CS01A/02A/04A H Series 6. 2 Page write The page write mode allows up to 8 bytes to be written in a single write operation in the S-24CS01A/02A and 16 bytes to be written in a single write operation in the S-24CS04A. Basic data transmission procedure is the same as that in the "Byte Write". But instead of generating a stop condition, the master transmits 8-bit write data up to 8 bytes before the page write. When the S-24CS01A/02A/04A receives a 7-bit device address and a 1-bit read / write instruction code set to "0", following a start condition, it generates an acknowledge. Then the S-24CS01A/02A/04A receives an 8-bit word address, and responds with an acknowledge. After the S- 24CS01A/02A/04A receives 8-bit write data and responds with an acknowledge, it receives 8-bit write data corresponding to the next word address, and generates an acknowledge. The S-24CS01A/02A/04A repeats reception of 8-bit write data and generation of acknowledge in succession. The S-24CS01A/02A/04A can receive as many write data as the maximum page size. Receiving a stop condition initiates a write cycle of the area starting from the designated memory address and having the page size equal to the received write data. Remark1. A0 is P0 in the S-24CS04A. 2. W7 is optional in the S-24CS01A. S T A R T 1 0 1 0 W R I T E S T O P DEVICE ADDRESS WORD ADDRESS (n) R W M S B SDA LINE A2 A1 A0 A C K L S B A C K A C K
0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D7 D0
A C K ADR INC ADR INC A C K DATA (n) DATA (n+1) DATA (n+x) W7 W6 W5 W4 W3 W2 W1 W0 ADR INC Figure 13 Page Write In S-24CS01A/02A, the lower 3 bits of the word address are automat ically incremented every time when the S-24CS01A/02A receives 8-bit write data. If the size of t he write data exceeds 8 bytes, the upper 5 bits of the word address remain unchanged, and the lower 3 bits are rolled over and previously received data will be overwritten. In S-24CS04A, the lower 4 bits of the word address are automatically incremented every time when the S-24CS04A receives 8-bit write data. If the size of the write data exceeds 16 bytes, the upper 4 bits of the word address and page address (P0) remain unchanged, and the lower 4 bits are rolled over and previously received data will be overwritten.
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM S-24CS01A/02A/04A H Series Rev.3.1_03 6. 3 Write protect Write protect is available in the S-24CS01A/02A /04A. When the WP pin is connected to the V CC, write operation to memory area is forbidden at all. When the WP pin is connected to the GND, the write prot ect is invalid, and write operation in all memory area is available. Fix the level of the WP pin from the rising edge of SCL for loading the last write data (D0) until the end of the write time (10 ms max.). If the WP pin changes during this time, the address data being written at this time is not guaranteed. There is no need for using write protect, the WP pin should be connected to the GND. The write protect is valid in the operating voltage range. SDA WP SCL Acknowledge WP Pin Fixed Period Stop Condition Start Condition Write Data tWR Figure 14 WP Pin Fixed Period 6. 4 Acknowledge polling Acknowledge polling is used to know the completion of the write cycle in the S-24CS01A/02A/04A. After the S-24CS01A/02A/04A receives a stop condition and onc e starts the write cycle, all operations are forbidden and no response is made to the signal transmitted by the master device. Accordingly the master device can recognize the comple tion of the write cycle in the S-24CS01A/02A/04A by detecting a response from the slave device after transmitting the start condition, the device address and the read/write instruction code to the S-24CS01A/02A/04A, namely to the slave devices. That is, if the S-24CS01A/02A/04A does not generate an acknowledge, the write cycle is in progress and if the S-24CS01A/02A/04A generates an acknowledge, the write cycle has been completed. Keep the level of the WP pin fixed until acknowledge is confirmed. It is recommended to use the read instruction "1" as the read/write instruction code transmitted by the master device.
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM Rev.3.1_03 S-24CS01A/02A/04A H Series 7. Read 7. 1 Current address read Either in writing or in reading the S-24CS01A/02A/04A holds the last accessed memory address, internally incremented by one. The memory address is maintained as long as the power voltage is higher than the current address hold voltage VAH. The master device can read the data at the memory address of the current address pointer without assigning the word address as a result, when it recognizes the position of the address pointer in the S-24CS01A/02A/04A. This is called "Current Address Read". In the following the address counter in the S-24CS01A/02A/04A is assumed to be "n". When the S-24CS01A/02A/04A receives a 7-bit device address and a 1-bit read / write instruction code set to "1" following a start condition, it responds with an acknowledge. However, the page address (P0) in S-24CS04A becomes invalid and the memory address of the current address pointer becomes valid. Next an 8-bit data at the address "n" is sent from t he S-24CS01A/02A/04A synchronous to the SCL clock. The address counter is incremented at the falling edge of the SCL clock for the 8th bit data, and the content of the address counter becomes n +1. The master device outputs stop condition not an acknowledge ,the reading of S-24CS01A/02A/04A is ended. S T A R T 1 0 1 0 R E A D S T O P DEVICE ADDRESS R W M S B SDA LINE A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 A C K L S B ADR INC DATA NO ACK from Master Device Remark A0 is P0 in S-24CS04A. Figure 15 Current Address Read Attention should be paid to the following point on the recognition of the address pointer in the S-24CS01A/02A/04A. In the read operation the memory address counter in the S- 24CS01A/02A/04A is automatically incremented at every falling edge of the SCL clock for the 8th bit of the output data. In the write operation, on the other hand, the upper bits of the memory address (the upper bits of the word address and page address) *1 are left unchanged and are not incremented at the falling edge of the SCL clock for the 8th bit of the received data. *1. S-24CS01A/02A is the upper 5 bits of the word address. S-24CS04A is the upper 4 bits of the word address and the page address P0.
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM S-24CS01A/02A/04A H Series Rev.3.1_03 7. 2 Random read Random read is used to read the data at an arbitrary memory address. A dummy write is performed to load the memory address into the address counter. When the S-24CS01A/02A/04A receives a 7-bit device address and a 1-bit read / write instruction code set to "0" following a start condition, it responds with an acknowl edge. The S-24CS01A/02A/04A then receives an 8-bit word address and responds with an acknowledge. The memory address is loaded to the address counter in the S-24CS01A/02A/04A by these operations. Reception of write data does not follow in a dummy write whereas reception of write data follows in a byte write and in a page write. Since the memory address is loaded into the memory address counter by dummy write, the master device can read the data starting from the arbitrary memory address by tr ansmitting a new start condition and performing the same operation in the current address read. That is, when the S-24CS01A/02A/04A receives a 7-bit dev ice address and a 1-bit read / write instruction code set to "1", following a start condition signal, it responds with an acknowledge. Next, 8-bit data is transmitted from the S-24CS01A/02A/04A in synchronous to the SCL clock. The master device outputs stop condition not an acknowledge , the reading of S-24CS01A/02A/04A is ended. SDA LINE S T A R T W R I T E DEVICE ADDRESS WORD ADDRESS (n) M S B DUMMY WRITE S T A R T R E A D DEVICE ADDRESS M S B A C K L S B NO ACK from Master Device S T O P ADR INC DATA A C K A C K L S B R W R W Remark1. A0 is P0 in the S-24CS04A. 2. W7 is optional in the S-24CS01A. 1 0 1 0 A2 A1 A0 0 W7 W6 W5 W4 W3 W2 W1 W0 1 0 1 0 A2 A1 A0 1 D7 D6 D5 D4 D3 D2 D1 D0 Figure 16 Random Read
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM Rev.3.1_03 S-24CS01A/02A/04A H Series 7. 3 Sequential read When the S-24CS01A/02A/04A receives a 7-bit device address and a 1-bit read / write instruction code set to "1" following a start condition both in current and random read operations, it responds with an acknowledge. An 8-bit data is then sent from the S-24CS01A/02A/04A synchronous to the SCL clock and the address counter is automatically incremented at the falling edge of the SCL clock for the 8th bit data. When the master device responds with an acknowledge, the data at the next memory address is transmitted. Response with an acknowledge by the master device has the memory address counter in the S-24CS01A/02A/04A incremented and makes it possible to read data in succession. This is called "Sequential Read". The master device outputs stop condition not an acknowledge , the reading of S-24CS01A/02A/04A is ended. Data can be read in succession in the sequential read mode. When the memory address counter reaches the last word address, it rolls over to the first memory address. R E A D S T O P DEVICE ADDRESS R W ADR INC A C K A C K A C K ADR INC A C K ADR INC SDA LINE DATA(n) D7 D0 D7 D0D7 D0 D7 D0 DATA (n+1) DATA (n+2) DATA (n+x) NO ACK from Master Device ADR INC Figure 17 Sequential Read
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM S-24CS01A/02A/04A H Series Rev.3.1_03 8. Address increment timing The timing for the automatic address incr ement is the falling edge of the SCL clock for the 8th bit of the read data in read operation and the falling edge of the SCL clock for the 8th bit of the received data in write operation. SCL SDA R / W=1 Address Increment 891 89 D7 Output D0 OutputACK Output Figure 18 Address Increment Timing in Reading SCL SDA R / W=0 891 89 D7 Input D0 InputACK Output ACK Output Address Increment Figure 19 Address Increment Timing in Writing Write Protect Function during the Low Power Supply Voltage The S-24CS01A/02A/04A has a detection circuit for low power voltage. The detection circuit cancels a write instruction when the power voltage is low or the power switch is on. The detection voltage is 1.75 V typically and the release voltage is 2.05 V typically, the hysteresis of approximate 0.3 V thus exists. (See Figure 20.) When a low power voltage is detected, a write instruction is canceled at the reception of a stop condition. When the power voltage lowers during a data transmission or a write operation, the data at the address of the operation is not assured. Power supply voltage Write Instruction cancel Release voltage (+VDET) 2.05 V typ. Detection voltage (-VDET) 1.75 V typ. Hysteresis width
0.3 V approximately
Figure 20 Operation during Low Power Supply Voltage
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM S-24CS01A/02A/04A H Series Rev.3.1_03 4. Acknowledge check The I2C-bus protocol includes an acknowledge check functi on as a handshake function to prevent a communication error. This function allows detection of a communication failure during data communication between the microprocessor and S-24CS01A/02A/04A. This function is effe ctive to prevent malfunction, so it is recommended to perform an acknowledge check on the microprocessor side. 5. Built-in power-on-clear circuit S-24CS01A/02A/04A has a built-in power-on-clear circuit that initializes the S-24CS01A/02A/04A. Unsuccessful initialization may cause a malfunction. For the power-on- clear circuit to operate normally, the following conditions must be satisfied for raising the power supply voltage. 5. 1 Raising power supply voltage Raise the power supply voltage, starting at 0.2 V maximum, so that the voltage reaches the power supply voltage to be used within the time defined by tRISE as shown in Figure 26. For example, when the power supply voltage to be used is 5.0 V, t RISE is 200 ms as shown in Figure 27. The power supply voltage must be raised within 200 ms. 0.2 V VINIT (Max.) tINIT *2 (Max.) tRISE (Max.) Power supply voltage (V CC)
0 V*1
*1. 0 V means there is no difference in potential between the VCC pin and the GND pin of the S-24CS01A/02A/04A. *2. tINIT is the time required to initialize t he S-24CS01A/02A/04A. No instructions are accepted during this time. Figure 26 Raising Power Supply Voltage
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM Rev.3.1_03 S-24CS01A/02A/04A H Series Rise time (tRISE) Max. [ms] Power supply voltage (VCC) [V] 5.0 4.0 3.0 2.0 100 150 200 For example: If your E2PROM supply voltage = 5.0 V, raise the power supply voltage to 5.0 V within 200 ms. Figure 27 Raising Time of Power Supply Voltage When initialization is successfully completed via the power-on-clear circuit, the S-24CS01A/02A/04A enters the standby status. If the power-on-clear circuit does not operate, the following are the possible causes. (1) Because the S-24CS01A/02A/04A has not been initialized, an instruction formerly input is valid or an instruction may be inappropriately recognized. In this case, writing may be performed. (2) The voltage may have dropped due to power off while the S-24CS01A/02A/04A is being accessed. Even if the microprocessor is reset due to the low power voltage, the S-24CS01A/02A/04A may malfunction unless the power- on-clear operation conditions of S-24CS01A/02A/04A are satisfied. For the power-on-clear operation conditions of S-24CS01A/02A/04A, refer to 5. 1 Raising power supply voltage. If the power-on-clear circuit does not operate, match the phase (reset) so that the internal S-24CS01A/02A/04A circuit is normally reset. The statuses of the S-24CS01A/02A/04A immediately after the power-on-clear circuit operates and when phase is matched (reset) are the same.
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM S-24CS01A/02A/04A H Series Rev.3.1_03 5. 2 Wait for the initialization sequence to end The S-24CS01A/02A/04A executes initialization during the time that the supply voltage is increasing to its normal value. All instructions must wait until after initialization. The relationship between the initialization time (t INIT) and rise time (tRISE) is shown in Figure 28. Rise time (tRISE) [s] E2PROM initialization time (tINIT) Max. [s] 100 m 10 m 1.0 m 100 μ 10 μ 1.0 μ 1.0 μ 10 μ 100 μ 1.0 m 10 m 100 m Figure 28 Initialization Time of S-24CS01A/02A/04A
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM S-24CS01A/02A/04A H Series Rev.3.1_03 8. S-24CS01A/02A/04A operation in case that th e stop condition is received during write operation before receiving the defined data value (less than 8-bit) to SCL pin When the S-24CS01A/02A/04A receives the stop condition signal compulsorily, during receiving 1 byte of write data, “write” operation is aborted. When the S-24CS01A/02A/04A receives the stop condition si gnal after receiving 1 byte or more of data for “page write”, 8-bit of data received normally before receiving the stop condition signal can be written. 9. S-24CS01A/02A/04A operation and write data in case that write data is input more than defined page size at “page write” When write data is input more than defined page size at page write operation, for example, S-24CS04A (which can be executed 16-byte page write) is received data more than 17 byte, 8-bit data of the 17th byte is over written to the first byte in the same page. Data over the capacity of page address cannot be written. 10. Severe environments Absolute maximum ratings: Do not operate these ICs in excess of the absolute maximum ratings (as listed on the data sheet). Exceeding the supply voltage rating can cause latch-up. Perform operations after confirming the detailed operation condition in the data sheet. Operations with moisture on the S-24CS01A/02A/04A pins may occur malfunction by short-circuit between pins. Especially, in occasions like picking the S-24CS01A/02A/04A up from low temperature tank during the evaluation. Be sure that not remain frost on S-24CS01A/02A/04A pin to prevent malfunction by short-circuit. Also attention should be paid in using on environment, which is easy to dew for the same reason. Precaution
- Do not apply an electrostatic discharge to this IC that ex ceeds the performance ratings of the built-in electrostatic protect circuit.
- ABLIC Inc. claims no responsibility for any and all disputes ar ising out of or in connection with any infringement of the products including this IC upon patents owned by a third party.
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM Rev.3.1_03 S-24CS01A/02A/04A H Series Product Name Structure 1. Product Name S-24CS0xA xx - xx H - U Environmental code U: Lead-free (Sn 100%), halogen-free Operation temperature H: −40°C to +105°C IC direction in tape specification TB: 8-Pin SOP (JEDEC), 8-Pin TSSOP TF: TMSOP-8 Package code (abbreviation) FJ: 8-Pin SOP (JEDEC) FT: 8-Pin TSSOP FM: TMSOP-8 Product name S-24CS01A: 1 Kbit S-24CS02A: 2 Kbit Remark Please contact our sales office for products with product name structure other than those specified above. 2. Package Package Name Drawing Code Package Tape Reel 8-Pin SOP (JEDEC) FJ008-A-P-SD FJ008-D-C-SD FJ008-D-R-S1 8-Pin TSSOP FT008-A-P-SD FT008-E-C-SD FT008-E-R-S1 TMSOP-8 FM008-A-P-SD FM 008-A-C-SD FM008-A-R-SD
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Disclaimers (Handling Precautions) 1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and application circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice. 2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. ABLIC Inc. is not responsible for damages caused by the reasons other than th e products described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use of the information described herein. 3. ABLIC Inc. is not responsible for damages ca used by the incorrect information described herein. 4. Be careful to use the products within their specified ranges. Pay special attention to the absolute maximum ratings, operation voltage range and electrical characteristics, etc. ABLIC Inc. is not responsible for damages caused by failures and / or accidents, etc. that occur due to the use of the products outside their specified ranges. 5. When using the products, confirm their applications, and the laws and regulations of the region or country where they are used and verify suitability, safety and other factors for the intended use. 6. When exporting the products, comply with the Foreig n Exchange and Foreign Trade Act and all other export-related laws, and follow the required procedures. 7. The products must not be used or pr ovided (exported) for the purposes of the development of weapons of mass destruction or military use. ABLIC Inc. is not responsible for any provision (e xport) to those whose purpose is to develop, manufacture, use or store nuclear, biological or chemical weapons, missiles, or other military use. 8. The products are not designed to be us ed as part of any device or equipment that may affect the human body, human life, or assets (such as medical equipment, disaster pr evention systems, security systems, combustion control systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment, aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses. Do not apply the products to the above listed devices and equipments without prior written permission by ABLIC Inc. Especially, the products cannot be us ed for life support devices, devices im planted in the human body and devices that directly affect human life, etc. Prior consultation with our sales office is required when considering the above uses. ABLIC Inc. is not responsible for damages caused by unauthorized or unspecified use of our products. 9. Semiconductor products may fail or malfunction with some probability. The user of the products should therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread prevention measures, and ma lfunction prevention to prevent accidents causing injury or death, fires and social damage, etc. that may ensue from the products' failure or malfunction. The entire system must be sufficiently evaluated and applied on customer's own responsibility. 10. The products are not designed to be radiation-proof. T he necessary radiation measures should be taken in the product design by the customer depending on the intended use. 11. The products do not affect human health under normal us e. However, they contain chemical substances and heavy metals and should therefore not be put in the mouth. The fr acture surfaces of wafers and chips may be sharp. Be careful when handling these with the bare hands to prevent injuries, etc. 12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used. 13. The information described herein contains copy right information and know-how of ABLIC Inc. The information described herein does not convey any lic ense under any intellectual property rights or any other rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this document described herein for the purpose of disclosing it to a third-party without the express permission of ABLIC Inc. is strictly prohibited. 14. For more details on the information de scribed herein, contact our sales office. 2.2-2018.06 www.ablic.com