DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 29
Technical content
www.ablicinc.com BATTERY PROTECTION IC FOR 3-SERIAL- OR 4-SERIAL-CELL PACK © ABLIC Inc., 2002-2016 Rev.5.2_01 The S-8254A Series is a protection IC for 3-serial- or 4-serial-cell lithium-ion / lithium polymer rechargeable batteries and includes a high-accuracy voltage detector and delay circuit. The S-8254A Series protects both 3-serial or 4-serial cells using the SEL pin for switching. Features (1) High-accuracy voltage detection for each cell Overcharge detection voltage n (n 1 to 4) 3.9 V to 4.4 V (50 mV step) Accuracy 25 mV Overcharge release voltage n (n 1 to 4) 3.8 V to 4.4 V *1 Accuracy 50 mV Overdischarge detection voltage n (n 1 to 4) 2.0 V to 3.0 V (100 mV step) Accuracy 80 mV Overdischarge release voltage n (n 1 to 4) 2.0 V to 3.4 V *2 Accuracy 100 mV (2) Three-level overcurrent protection Overcurrent detection voltage 1 0.05 V to 0.30 V (50 mV step) Accuracy 25 mV Overcurrent detection voltage 2 0.5 V Accuracy 100 mV Overcurrent detection voltage 3 V VC1 1.2 V Accuracy 300 mV (3) Delay times for overcharge detection, overdischa rge detection and overcurrent detection 1 can be set by external capacitors (delay times for overcurrent detection 2 and 3 are fixed internally). (4) Switchable between a 3-serial cell and 4-serial cell using the SEL pin (5) Charge/discharge operation can be controlled via the control pins. (6) High-withstand voltage Absolute maximum rating : 26 V (7) Wide operating voltage range 2 V to 24 V (8) Wide operating temperature range 40C to 85C (9) Low current consumption During operation 30 A max. (25C) During power-down 0.1 A max. (25C) (10) Lead-free, Sn100%, halogen-free *1. Overcharge hysteresis voltage n (n 1 to 4) can be selected as 0 V or from a range of 0.1 V to 0.4 V in 50 mV steps. (Overcharge hysteresis voltage Overcharge detection voltage Overcharge release voltage) *2. Overdischarge hysteresis voltage n (n 1 to 4) can be selected as 0 V or from a range of 0.2 V to 0.7 V in 100 mV steps. (Overdischarge hysteresis voltage Overdischarge release voltage Overdischarge detection voltage) *3. Refer to “ Product Name Structure” for details. Applications Lithium-ion rechargeable battery packs Lithium polymer rechargeable battery packs Package 16-Pin TSSOP www.ablic.com
BATTERY PROTECTION IC FOR 3-SERIAL- OR 4-SERIAL-CELL PACK S-8254A Series Rev.5.2_01 Block Diagram COP VDD VSS VMP DOP VINI CDT VC1 VC2 VC3 CTL SEL VC4 DOP, COP, RVMD, RVMS Control Circuit Delay Circuit Delay Circuit Delay Circuit Delay Circuit1 M 900 k CCT 200 nA Remark 1. Diodes in the figure are parasitic diodes. 2. Numerical values are typical values. Figure 1
BATTERY PROTECTION IC FOR 3- SERIAL- OR 4-SERIAL-CELL PACK Rev.5.2_01 S-8254A Series Product Name Structure 1. Product Name S-8254A xx FT - TB - x Environmental code U: Lead-free (Sn 100%), halogen-free S: Lead-free, halogen-free G: Lead-free (for details, please contact our sales office) IC direction in tape specifications *1 Package code FT: 16-Pin TSSOP Serial code *2 Sequentially set from AA to ZZ *1. Refer to the tape drawing. *2. Refer to “3. Product Name List”. 2. Package Package name Package Tape Reel 16-Pin TSSOP Environmental code = G, S FT016-A-P-SD FT016-A-C-SD FT016-A-R-SD Environmental code = U FT016-A-P-SD FT016-A-C-SD FT016-A-R-S1
BATTERY PROTECTION IC FOR 3-SERIAL- OR 4-SERIAL-CELL PACK S-8254A Series Rev.5.2_01 3. Product Name List Table 1 Product name / Item Overcharge detection voltage [VCU] Overcharge release voltage [VCL] Overdischarge detection voltage [VDL] Overdischarge release voltage [VDU] Overcurrent detection voltage 1 [VIOV1]
0 V battery
Remark 1. Please contact our sales office for the products with the detection voltage value other than those specified above. 2. x: G or U y: S or U 3. Please select products of environmental code = U for Sn 100%, halogen-free products.
BATTERY PROTECTION IC FOR 3- SERIAL- OR 4-SERIAL-CELL PACK Rev.5.2_01 S-8254A Series Pin Configuration 16-Pin TSSOP Top view COP VMP DOP VINI CDT CCT VSS NC VDD VC1 VC2 VC3 VC4 CTL SEL NC Figure 2 Table 2 Pin No. Symbol Description
1 COP FET gate connection pin for charge control (Nch open drain output)
2 VMP Pin for voltage detection between VC1 and VMP (Pin for overcurrent 3
detection)
3 DOP FET gate connection pin for discharge control FET (CMOS output)
4 VINI Pin for voltage detection between VSS and VINI (Pin for overcurrent detection
1,2)
5 CDT Capacitor connection pin for delay for overdischarge detection, delay for
6 CCT Capacitor connection pin for delay for overcharge current
7 VSS Input pin for negative power supply,
Connection pin for battery 4’s negative voltage
8 NC *1 No connection
9 NC *1 No connection
10 SEL Pin for switching 3-series or 4-series cell
VSS level: 3-series cell, VDD level : 4-series cell
11 CTL Control of charge FET and discharge FET
12 VC4 Connection pin for battery 3’s negative voltage,
Connection pin for battery 4’s positive voltage
13 VC3 Connection pin for battery 2’s negative voltage,
Connection pin for battery 3’s positive voltage
14 VC2 Connection pin for battery 1’s negative voltage,
Connection pin for battery 2’s positive voltage
15 VC1 Connection pin for battery 1’s positive voltage
16 VDD Input pin for positive power supply,
Connection pin for battery 1’s positive voltage *1. The NC pin is electrically open. The NC pin can be connected to VDD or VSS.
BATTERY PROTECTION IC FOR 3-SERIAL- OR 4-SERIAL-CELL PACK S-8254A Series Rev.5.2_01 Absolute Maximum Ratings Table 3 (Ta 25C unless otherwise specified) Item Symbol Applied pin Absolute Maximum Ratings Unit Input voltage between VDD and VSS V DS VSS 0.3 to VSS 26 V Input pin voltage V IN VC1, VC2, VC3, VC4, CTL, SEL, CCT, CDT, VINI V SS 0.3 to VDD 0.3 V VMP pin input voltage V VMP VMP VSS 0.3 to VSS 26 V DOP pin output voltage V DOP DOP VSS 0.3 to VDD 0.3 V COP pin output voltage V COP COP VSS 0.3 to VSS 26 V Power dissipation P D 400 (When not mounted on board) mW 1100*1 mW Operating ambient temperature T opr 40 to 85 C Storage temperature T stg 40 to 125 C *1. When mounted on board [Mounted board] (1) Board size : 114.3 mm 76.2 mm t1.6 mm (2) Board name : JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. 0 50 100 150 800 400 Power Dissipation (PD) [mW] Ambient Temperature (Ta) [C] 1000 600 200 1200 Figure 3 Power Dissipation of Package (When Mounted on Board)
BATTERY PROTECTION IC FOR 3- SERIAL- OR 4-SERIAL-CELL PACK Rev.5.2_01 S-8254A Series Electrical Characteristics Table 4 (1 / 2) (Ta 25C unless otherwise specified) Item Symbol Conditions Min. Typ. Max. Unit Test circuit [ DETECTION VOLTAGE ] Overcharge detection voltage n (n 1, 2, 3, 4) VCUn 3.9 V to 4.4 V, Adjustable VCUn 0.025 VCUn VCUn 0.025 V 2 Overcharge release voltage n (n 1, 2, 3, 4) VCLn 3.8 V to 4.4 V, Adjustable VCL VCU VCLn 0.05 VCLn VCLn 0.05 V 2 VCL VCU VCLn 0.025 VCLn VCLn 0.025 V 2 Overdischarge detection voltage n (n 1, 2, 3, 4) VDLn 2.0 V to 3.0 V, Adjustable VDLn 0.08 VDLn VDLn 0.08 V 2 Overdischarge release voltage n (n 1, 2, 3, 4) VDUn 2.0 V to 3.4 V, Adjustable VDL VDU VDUn 0.10 VDUn VDUn 0.10 V 2 VDL VDU VDUn 0.08 VDUn VDUn 0.08 V 2 Overcurrent detection voltage 1 V IOV1 0.05 V to 0.3 V, Adjustable VIOV1 0.025 VIOV1 VIOV1 0.025 V 2 Overcurrent detection voltage 2 V IOV2 0.4 0.5 0.6 V 2 Overcurrent detection voltage 3 V IOV3 VVC1 1.5 VVC1 1.2 VVC1 0.9 V 2 Temperature coefficient 1 *1 T COE1 Ta 0°C to 50°C *3 1.0 0 1.0 mV / °C 2 Temperature coefficient 2 *2 T COE2 Ta 0°C to 50°C *3 0.5 0 0.5 mV / °C 2 [ DELAY TIME ] Overcharge detection delay time t CU CCT pin capacitance 0.1 F 0.5 1.0 1.5 s 3 Overdischarge detection delay time tDL CDT pin capacitance 0.1 F 50 100 150 ms 3 Overcurrent detection delay time 1 tIOV1 CDT pin capacitance 0.1 F 5 10 15 ms 3 Overcurrent detection delay time 2 tIOV2 0.4 1 1.6 ms 3 Overcurrent detection delay time 3 tIOV3 FET gate capacitance 2000 pF 100 300 600 s 3 [ 0 V BATTERY CHARGE FUNCTION ]
0 V battery charge
starting charger voltage V0CHA 0 V battery charging available 0.8 1.5 V 4 inhibition battery voltage V0INH 0 V battery charging unavailable 0.4 0.7 1.1 V 4 [ INTERNAL RESISTANCE ] Resistance between VMP and VDD RVMD 0.5 1 1.5 M 5 Resistance between VMP and VSS RVMS 450 900 1800 k 5
BATTERY PROTECTION IC FOR 3-SERIAL- OR 4-SERIAL-CELL PACK S-8254A Series Rev.5.2_01 Table 4 (2 / 2) (Ta 25C unless otherwise specified) Item Symbol Conditions Min. Typ. Max. Unit Test circuit [ INPUT VOLTAGE ] Operating voltage between VDD and VSS V DSOP Output voltage of DOP and COP fixed 2 24 V 2 CTL input voltage “H” V CTLH VDD 0.8 V 2 CTL input voltage “L” V CTLL VDD 0.2 V 2 SEL input voltage “H” V SELH VDD 0.8 V 2 SEL input voltage “L” V SELL VDD 0.2 V 2 [ INPUT CURRENT ] Current consumption during operation IOPE V1 V2 V3 V4 3.5 V 12 30 A 1 Current consumption during power-down IPDN V1 V2 V3 V4 1.5 V 0.1 A 1 VC1 pin current I VC1 V1 V2 V3 V4 3.5 V 1.5 3 A 5 VC2 pin current I VC2 V1 V2 V3 V4 3.5 V 0.3 0 0.3 A 5 VC3 pin current I VC3 V1 V2 V3 V4 3.5 V 0.3 0 0.3 A 5 VC4 pin current I VC4 V1 V2 V3 V4 3.5 V 0.3 0 0.3 A 5 CTL pin current “H” I CTLH V1 V2 V3 V4 3.5 V, VCTL VDD 0.1 A 5 CTL pin current “L” I CTLL V1 V2 V3 V4 3.5 V, VCTL VSS 0.4 0.2 A 5 SEL pin current “H” I SELH V1 V2 V3 V4 3.5 V, VSEL VDD 0.1 A 5 SEL pin current “L” I SELL V1 V2 V3 V4 3.5 V, VSEL VSS 0.1 A 5 [ OUTPUT CURRENT ] COP pin leakage current I COH VCOP 24 V 0.1 A 5 COP pin sink current I COL VCOP VSS 0.5 V 10 A 5 DOP pin source current I DOH VDOP VDD 0.5 V 10 A 5 DOP pin sink current I DOL VDOP VSS 0.5 V 10 A 5 *1. Voltage temperature coefficient 1 : Overcharge detection voltage *2. Voltage temperature coefficient 2 : Overcurrent detection voltage 1 *3. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by design, not tested in production.
BATTERY PROTECTION IC FOR 3- SERIAL- OR 4-SERIAL-CELL PACK Rev.5.2_01 S-8254A Series Test Circuits This chapter describes how to test the S-8254A Series when a 4-serial cell is selected by setting the SEL pin to the VDD level. When a 3-serial cell is selected by setting the SEL pin to the VSS level, short the power supply V4. 1. Current Consumption during Operation, Current Consumption during Power-down (Test circuit 1) 1. 1 Current Consumption during operation (IOPE) The current at the VSS pin when V1 V2 V3 V4 3.5 V and V VMP V DD is the current consumption during operation (IOPE). 1. 2 Current Consumption during power-down (IPDN) The current at the VSS pin when V1 V2 V3 V4 1.5 V and VVMP VSS is the current consumption during power-down (IPDN). 2. Overcharge Detection Voltage, Overcharge Re lease Voltage, Overdischarge Detection Voltage, Overdischarge Release Voltage, Overcurrent Detect ion Voltage 1, Overcurrent Detection Voltage 2, Overcurrent Detection Voltage 3, CTL Input Voltage “H”, CTL Input Voltage “L”, SEL Input Voltage “H”, SEL Input Voltage “L” (Test circuit 2) Confirm that the COP pin and DOP pin are low (V DD 0.1 V or lower) when V VMP VSEL VDD, VINI VCTL VSS, the CCT pin is open, the CDT pin is open, and V1 V2 V3 V4 3.5 V (this status is referred to as the initial status). 2. 1 Overcharge Detection Voltage (VCU1), Overcharge Release Voltage (VCL1) The overcharge detection voltage (V CU1) is the voltage of V1 when the voltage of the COP pin is “H” (VDD 0.9 V or more) after the V1 voltage has been grad ually increased starting at the initial status. The overcharge release voltage (VCL1) is the voltage of V1 when the voltage at the COP pin is “L” after the V1 voltage has been gradually decreased. 2. 2 Overdischarge Detection Voltage (VDL1), Overdischarge Release Voltage (VDU1) The overdischarge detection voltage (VDL1) is the voltage of V1 when the voltage of the DOP pin is “H” after the V1 voltage has been gradually decreased star ting at the initial status. The overdischarge release voltage (VDU1) is the voltage of V1 when the voltage at the DOP pin is “L” after the V1 voltage has been gradually increased. When the voltage of Vn (n 2 to 4) is changed, the overcharge detection voltage (V CUn), overcharge release voltage (V CLn), overdischarge detection voltage (V DLn), and overdischarge release voltage (VDUn) can be determined in the same way as when n 1. 2. 3 Overcurrent Detection Voltage 1 (VIOV1) Overcurrent detection voltage 1 (V IOV1) is the voltage of the VINI pi n when the voltage of the DOP pin is “H” after the VINI pin voltage has been gradually increased starting at the initial status. 2. 4 Overcurrent Detection Voltage 2 (VIOV2) Overcurrent detection voltage 2 (V IOV2) is the voltage of the VINI pi n when the voltage of the DOP pin is “H” after the voltage of the CDT pin was set to VSS following the initial status and the voltage of the VINI pin has been gradually decreased. 2. 5 Overcurrent Detection Voltage 3 (VIOV3) Overcurrent detection voltage 3 (V IOV3) is the voltage difference between V VC1 and VVMP (VVC1 VVMP) when the voltage of the DOP pin is “H” after the VMP voltage has been gradually decreased starting at the initial status.
BATTERY PROTECTION IC FOR 3-SERIAL- OR 4-SERIAL-CELL PACK S-8254A Series Rev.5.2_01 2. 6 CTL Input Voltage “H” (VCTLH), CTL Input Voltage “L” (VCTLL) The CTL input voltage “H” (VCTLH) is the voltage of CTL when the voltages at the COP and DOP pins are “H” after the CTL voltage has been gradually increased starting at the initial status. The CTL input voltage “L” (VCTLL) is the voltage of CTL when the voltages at the COP and DOP pins are “L” after the CTL voltage has been gradually decreased. 2. 7 SEL Input Voltage “H” (VSELH), SEL Input Voltage “L” (VSELL) Apply 0 V to V4 in the initial status and confirm that the DOP pin is “H”. The SEL input voltage “L” (VSELL) is the voltage of the SEL pin when the voltage at the DOP pin is “L” after the SEL voltage has been gradually decreased. The SEL input voltage “H” (VSELH) is the voltage of the SEL pin when the voltage of the DOP pin is “H” after the SEL voltage has been gradually increased. 3. Overcharge Detection Delay Time, Overdischarge Detection Delay Time, Overcurrent Detection Delay Time 1, Overcurrent Detection Delay Time 2, Overcurrent Detection Delay Time 3 (Test circuit 3) Confirm that the COP pin and DOP pin are “L” when V VMP VDD, VINI VSS, and V1 V2 V3 V4 3.5 V (this status is referred to as the initial status). 3. 1 Overcharge Detection Delay Time (tCU) The overcharge detection delay time (tCU) is the time it takes for the voltage of the COP pin to change from “L” to “H” after the voltage of V1 is instantaneously changed to 4.5 V from the initial status. 3. 2 Overdischarge Detection Delay Time (tDL) The overdischarge detection delay time (t DL) is the time it takes for the voltage of the DOP pin to change from “L” to “H” after the voltage of V1 is instantaneously changed to 1.5 V from the initial status 3. 3 Overcurrent Detection Delay Time 1 (tIOV1) Overcurrent detection delay time 1 (t IOV1) is the time it takes for the voltage of the DOP pin to change from “L” to “H” after the voltage of the VINI pin is instantaneously changed to 0.4 V from the initial status. 3. 4 Overcurrent Detection Delay Time 2 (tIOV2) Overcurrent detection delay time 2 (t IOV2) is the time it takes for the voltage of the DOP pin to change from “L” to “H” after the voltage of the VINI pin is instantaneously changed to V IOV2 max. 0.2 V from the initial status. 3. 5 Overcurrent Detection Delay Time 3 (tIOV3) Overcurrent detection delay time 3 (t IOV3) is the time it takes for the voltage of the DOP pin to change from “L” to “H” after the voltage of the VMP pin is instantaneously changed to VIOV3 min. 0.2 V from the initial status.
BATTERY PROTECTION IC FOR 3- SERIAL- OR 4-SERIAL-CELL PACK Rev.5.2_01 S-8254A Series 4. 0 V Battery Charge Starting Charger Voltage (Product with 0 V Battery Charge Function), 0 V Battery Charge Inhibition Battery Voltage (Pr oduct with 0 V Battery Charge Inhibition Function) (Test circuit 4) Either the 0 V battery charge starting charger voltage or the 0 V battery charge inhibition battery voltage is applied to each product according to the 0 V battery charge function. 4. 1 0 V Battery Charge Starting Charger Voltage (V 0CHA) (Product with 0 V Battery Charge Function) The starting condition is V1 V2 V3 V4 0 V for a product in which 0 V battery charging is available. The COP pin voltage should be lower than V 0CHA max. 1 V when the VMP pin voltage VVMP V0CHA max. 4. 2 0 V Battery Charge Inhibition Battery Voltage (V 0INH) (Product with 0 V Battery Charge Inhibition Function) The starting condition is V1 V2 V3 V4 V0INH for a product in which 0 V battery charging is inhibited. The COP pin voltage should be higher than V VMP 1 V when the VMP pin voltage V VMP 24 V. 5. Resistance between VMP and VDD, Resistance between VMP and VSS, VC1 Pin Current, VC2 Pin Current, VC3 Pin Current, VC4 Pin Current, CTL pi n Current “H”, CTL Pin Current “L”, SEL Pin Current “H”, SEL Pin Current “L”, COP Pin Leakage Current, COP Pin Sink Current, DOP Pin Source Current, DOP Pin Sink Current (Test circuit 5) V VMP VSEL VDD, VINI VCTL VSS, V1 V2 V3 V4 3.5 V, and other pins left “open” (this status is referred to as the initial status). 5. 1 Resistance between VMP and VDD (RVMD) The resistance between VMP and VDD (R VMD) is obtained from R VMD VDD / I VMD using the current value of the VMP pin (IVMD) when VVMP is VSS after the initial status. 5. 2 Resistance between VMP and VSS (RVMS) The resistance between VMP and VSS (R VMS) is obtained from R VMS VDD / I VMS using the current value of the VMP pin (IVMS) when V1 V2 V3 V4 1.8 V after the initial status. 5. 3 VC1 Pin Current (IVC1), VC2 Pin Current (IVC2), VC3 Pin Current (IVC3), VC4 Pin Current (IVC4) At the initial status, the current that flows through the VC1 pin is the VC1 pin current (I VC1), the current that flows through the VC2 pin is the VC2 pin current (I VC2), the current that flows through the VC3 pin is the VC3 pin current (I VC3), and the current that flows through the VC4 pin is the VC4 pin current (IVC4). 5. 4 CTL pin Current “H” (ICTLH), CTL Pin Current “L” (ICTLL) In the initial status, the curr ent that flows through the CTL pi n is the CTL pin current “L” (I CTLL), after that, when VCTL VDD, the current that flows through the CTL pin is the CTL pin current “H” (ICTLH). 5. 5 SEL Pin Current “H” (ISELH), SEL Pin Current “L” (ISELL) In the initial status, the current that flows through the SEL pi n is the SEL pin current “H” (ISELH), after that, when VSEL VSS, the current that flows through the SEL pin is the SEL pin current “L” (ISELL).
BATTERY PROTECTION IC FOR 3-SERIAL- OR 4-SERIAL-CELL PACK S-8254A Series Rev.5.2_01 5. 6 COP Pin Leakage Current (ICOH), COP Pin Sink Current (ICOL) The COP pin sink current (ICOL) is the current that flows through the COP pin when V COP VSS 0.5 V after the initial status. After that, the current that flows through the COP pin when V1 V2 V3 V4 6 V and VCOP VDD is the COP pin leakage current (ICOH). 5. 7 DOP Pin Source Current (IDOH), DOP Pin Sink Current (IDOL) The DOP pin sink current (IDOL) is the current that flows through the DOP pin when V DOP VSS 0.5 V after the initial status. After that, the cu rrent that flows through the DOP pin when V VMP VDD 2 V and VDOP VDD 0.5 V is the DOP pin source current (IDOH). 1C O P 2V M P 3D O P 4V I N I
5 CDT
6 CCT
7 VSS
C1 = 0.1 F NC A Figure 4 Test Circuit 1 1C O P 2V M P 3D O P 4V I N I C1 = 0.1 F NC V V Figure 5 Test Circuit 2
BATTERY PROTECTION IC FOR 3- SERIAL- OR 4-SERIAL-CELL PACK Rev.5.2_01 S-8254A Series 1C O P 2V M P 3D O P 4V I N I C1 = 0.1 F NC C2 = 0.1 F C3 = 0.1 F V V Figure 6 Test Circuit 3 1C O P 2V M P 3D O P 4V I N I C1 = 0.1 F NC V Figure 7 Test Circuit 4 1C O P 2V M P 3D O P 4V I N I C1 = 0.1 F NC A A A A A A A A A Figure 8 Test Circuit 5
BATTERY PROTECTION IC FOR 3-SERIAL- OR 4-SERIAL-CELL PACK S-8254A Series Rev.5.2_01 Operation Remark Refer to “ Battery Protection IC Connection Example”. 1. Normal Status When the voltage of each of the batteries is in the range from V DLn to V CUn and the discharge current is lower than the specified value (the VINI pin voltage is lower than VIOV1 and VIOV2, and the VMP pin voltage is higher than VIOV3), the charging and discharging FETs are turned on. 2. Overcharge Status When the voltage of one of the batteries becomes higher than V CUn and the state continues for t CU or longer, the COP pin becomes high impedance. The COP pin is pulled up to the EB pin voltage by an external resistor, and the charging FET is turned o ff to stop charging. This is called the overcharge status. The overcharge status is released when one of the following two conditions holds. (1) T he voltage of each of the batteries becomes VCLn or lower. (2) T he voltage of each of the batteries is VCUn or lower, and the VMP pin voltage is 39 / 40 VDD or lower (a load is connected and discharging is started via the body diode of the charging FET). 3. Overdischarge Status When t he voltage of one of the batteries becomes lower than V DLn and the state continues for t DL or longer, the DOP pin voltage becomes VDD level, and the discharging FET is turned off to stop discharging. This is called the overdischarge status. 3. 1 Power-down Function When the overdischarge status is reache d, the VMP pin is pulled down to the V SS level by the internal R VMS resistor of the IC. When the VMP pin voltage is V DD / 2 or lower, the power-down function starts to operate and almost every circ uit in the S-8254A Series stops working. The conditions of each output pin are as follows. (1) COP pin : High-Z (2) DOP pin : V DD The power-down function is released when the following condition holds. (1) The VMP pin voltage is VDD / 2 or higher. The overdischarge status is released when the following two conditions hold. (1) In case the VMP pin voltage is VDD / 2 or higher and the VMP pin voltage is lower than VDD, the overdischarge status is released when the voltage of each of the batteries is VDUn or higher. (2) In case a charger is connected, the ov erdischarge hysteresis is released. And the overdischarge status is released when t he voltage of each of the batteries is V DLn or higher.
BATTERY PROTECTION IC FOR 3- SERIAL- OR 4-SERIAL-CELL PACK Rev.5.2_01 S-8254A Series 4. Overcurrent Status The S-8254A Series has three overcurrent detection levels (V IOV1, VIOV2, and VIOV3) and three overcurrent detection delay times (t IOV1, tIOV2, and tIOV3) corresponding to each overcurr ent detection level. When the discharging current becomes higher than the specified value (the voltage between V SS and VINI is greater than VIOV1) and the state continues for tIOV1 or longer, the S-8254A Series enters the overcurrent status, in which the DOP pin voltage becomes V DD level to turn off the discharging FET to stop discharging, the COP pin becomes high impedance and is pulled up to the EB pin voltage to turn off the charging FET to stop charging, and the VMP pin is pulled up to the V DD voltage by the internal resistor (R VMD). Operation of overcurrent detection level 2 (V IOV2) and overcurrent detecti on delay time 2 (t IOV2) is the same as for VIOV1 and tIOV1. In the overcurrent status, the VMP pin is pulled up to the V DD level by the internal resistor in the IC (R VMD resistor). The overcurrent status is released when the following condition holds. (1) The VMP pin voltage is V IOV3 or higher because a charger is connected or the load (30 M or more) is released. 5. 0 V Battery Charge Function Regarding the charging of a self-discharged battery (0 V battery), the S-8254A Series has two functions from which one should be selected. (1) 0 V battery charging is allowed (0 V battery charging is available.) When the charger voltage is higher than V0CHA, the 0 V battery can be charged. (2) 0 V battery charging is prohibited (0 V battery charging is unavailable.) When the battery voltage is V0INH or lower, the 0 V battery cannot be charged. Caution When the VDD pin voltage is lower than the minimum value of V DSOP, the operation of the S-8254A Series is not guaranteed. 6. Delay Time Setting The overcharge detection delay time (t CU) is determined by the external capacitor connected to the CCT pin. The overdischarge detection delay time (t DL) and overcurrent detection delay time 1 (t IOV1) are determined by the external capacitor connected to the CDT pin. Overcurrent detection delay times 2 and 3 (tIOV2, tIOV3) are fixed internally. min. typ. max. 7. CTL Pin The S-8254A Series has control pins. The CTL pin is used to control the COP and DOP pin output voltages. CTL pin takes precedence over the battery protection circuit. Table 5 Conditions Set by CTL Pin CTL Pin COP Pin DOP Pin High High-Z V DD Open High-Z V DD Low Normal status *1 Normal status *1 *1. The status is controlled by the voltage detector. Caution Please note unexpected behavior might occur when electrical potential difference between the CTL pin (‘L’ level) and VSS is generated through the external filter (RVSS and CVSS) as a result of input voltage fluctuations.
BATTERY PROTECTION IC FOR 3-SERIAL- OR 4-SERIAL-CELL PACK S-8254A Series Rev.5.2_01 8. SEL pin The S-8254A Series has control pins. The SEL pin is used to switch between 3-cell and 4-cell protection. When the SEL pin is low, overdischarge detection of the V4 cell is prohibited and an overdischarge is not detected even if the V4 cell is shorted, therefore, the V4 cell can be used for 3-cell protection. The SEL pin takes precedence over the battery protection circuit. Use the SEL pin at high or low. Table 6 Conditions Set by SEL Pin SEL Pin Condition High 4-cell protection Open Undefined Low 3-cell protection
BATTERY PROTECTION IC FOR 3- SERIAL- OR 4-SERIAL-CELL PACK Rev.5.2_01 S-8254A Series Timing Chart 1. Overcharge Detection and Overdischarge Detection VCUn VDUn VDLn VCLn High-Z VSS VDD VSS VSS VDD VEB VEB (n = 1 to 4) Battery voltage COP pin voltage 39 / 40VDD VMP pin voltage DOP pin voltage Charger connection Load connection Status*1 Overcharge detection delay time (tCU) High-Z 1 / 2VDD <3> Overdischarge detection delay time (tDL) *1. < 1 > : Normal status < 2 > : Overcharge status < 3 > : Overdischarge status < 4 > : Power-down status Remark The charger is assumed to charge with a constant current. V EB indicates the open voltage of the charger. Figure 9
BATTERY PROTECTION IC FOR 3-SERIAL- OR 4-SERIAL-CELL PACK S-8254A Series Rev.5.2_01 2. Overcurrent detection VCUn VDUn VDLn (n = 1 to 4) VCLn Battery voltage VHC VHD VDD DOP pin voltage VSS High-Z VEB VSS COP pin voltage High-Z High-Z VDD VSS VMP pin voltage VIOV3 VIOV2 VSS VINI pin voltage VDD VIOV1 Load connection Status*1 Overcurrent 1 detection delay time (tIOV1) Overcurrent 2 detection delay time (t IOV2) Overcurrent 3 detection delay time (t IOV3) *1. < 1 > : Normal status < 2 > : Overcurrent status Remark The charger is assumed to charge with a constant current. V EB indicates the open voltage of the charger. Figure 10
BATTERY PROTECTION IC FOR 3- SERIAL- OR 4-SERIAL-CELL PACK Rev.5.2_01 S-8254A Series Battery Protection IC Connection Example 1. 3-serial Cell EB RCOP RVMP RDOP RVINI CCDT CCCT EB 1C O P 2V M P 3D O P 4V I N I
- 4-serial Cell EB RCOP RVMP RDOP RVINI CCDT CCCT EB 1C O P 2V M P 3D O P 4V I N I
BATTERY PROTECTION IC FOR 3-SERIAL- OR 4-SERIAL-CELL PACK S-8254A Series Rev.5.2_01 Table 7 Constants for External Components Symbol Min. Typ. Max. Unit RVC1 *1 0 1 1 k RVC2 *1 0 1 1 k RVC3 *1 0 1 1 k RVC4 *1 0 1 1 k RDOP 2 5.1 10 k RCOP 0.1 1 1 M RVMP 1 5.1 10 k RCTL 1 1 100 k RVINI 1 1 100 k RSEL 1 1 100 k RSENSE 0 m RVSS *1 10 51 51 CVC1 *1 0 0.1 0.33 F CVC2 *1 0 0.1 0.33 F CVC3 *1 0 0.1 0.33 F CVC4 *1 0 0.1 0.33 F CCCT 0.01 0.1 F CCDT 0.07 0.1 F CVSS *1 2.2 2.2 10 F *1. Please set up a filter constant to be R VSS CVSS 51 F and to be R VC1 CVC1 = RVC2 CVC2 = RVC3 CVC3 = R VC4 CVC4 = RVSS CVSS. Caution 1. The above constants may be changed without notice. 2. It is recommended that filter constants between VDD and VSS should be set approximately to 112 F . e.g. CVSS RVSS 2.2 F 51 112 F Enough evaluation of transient power supply variation and overcurrent protection function in the actual application is needed to determine the proper constants. Contact our sales office in case the constants should be set to other than 112 F • or so. 3. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addi tion, the example of connection shown above and the constant do not guarantee proper operation. Perform thorough evaluation using the actual application to set the constant. Precautions The application conditions for the input voltage, output voltage, and load current should not exceed the package power dissipation. Batteries can be connected in any order, however, there may be cases when discharging cannot be performed when a battery is connected. In this ca se, short the VMP pin and VDD pin or connect the battery charger to return to the normal status. When an overcharged battery and an overdischarged batte ry intermix, the circuit is in both the overcharge and overdischarge statuses, so charging and discharging are not possible. Do not apply an electrostatic discharge to this IC that exceeds the performanc e ratings of the built-in electrostatic protection circuit. ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party.
BATTERY PROTECTION IC FOR 3- SERIAL- OR 4-SERIAL-CELL PACK Rev.5.2_01 S-8254A Series Characteristics (Typical Data) 1. Current Consumption 1. 1 IOPE vs. VDD 1. 2 I OPE vs. Ta 0 5 10 15 20 24 IOPE [A] VDD [V] 40 25 0 25 50 75 85 40IOPE [A] Ta [C] 1. 3 IPDN vs. VDD 1. 4 IPDN vs. Ta 0 5 10 15 20 24 0.01 0.00 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 IPDN [A] VDD [V] 40 25 0 25 50 75 85 0.01 0.00 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 IPDN [A] Ta [C] 2. Overcharge Detection / Release Voltage, Overdischarge Detection / Release Voltage, Overcurrent Detection Voltage, and Delay Times 2. 1 VCU vs. Ta 2. 2 V CL vs. Ta 40 25 0 25 50 75 85 4.330 4.325 4.335 4.340 4.345 4.350 4.355 4.360 4.365 4.370
4.375 VCU [V]
Ta [C] 40 25 0 25 50 75 85 4.10 4.12 4.14 4.16 4.18 4.20 VCL [V] Ta [C] 2. 3 VDU vs. Ta 2. 4 VDL vs. Ta 40 25 0 25 50 75 85 2.62 2.60 2.64 2.66 2.68 2.70 2.72 2.74 2.76 2.78
2.80 VDU [V]
Ta [C] 40 25 0 25 50 75 85 1.94 1.92 1.96 1.98 2.00 2.02 2.04 2.06 2.08 VDL [V] Ta [C]
BATTERY PROTECTION IC FOR 3-SERIAL- OR 4-SERIAL-CELL PACK S-8254A Series Rev.5.2_01 2. 5 VIOV1 vs. VDD 2. 6 VIOV1 vs. Ta 10 11 12 13 14 15 16 0.26 0.25 0.27 0.28 0.29 0.30 0.31 0.32 0.33 0.34
0.35 VIOV1 [V]
VDD [V] 40 25 0 25 50 75 85 0.280 0.275 0.285 0.290 0.295 0.300 0.305 0.310 0.315 0.320 0.325VIOV1 [V] Ta [C] 2. 7 VIOV2 vs. VDD 2. 8 VIOV2 vs. Ta 10 11 12 13 14 15 16 0.42 0.40 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58
0.60 VIOV2 [V]
VDD [V] 40 25 0 25 50 75 85 0.42 0.40 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 VIOV2 [V] Ta [C] 2. 9 VIOV3 vs. VDD 2. 10 VIOV3 vs. Ta 10 11 12 13 14 15 16 1.4 1.5 1.3 1.2 1.1 0.9 1.0 VIOV3 [V] VDD [V] 40 25 0 25 50 75 85 1.4 1.5 1.3 1.2 1.1 0.9 1.0 VIOV3 [V] Ta [C] 2. 11 tCU vs. CCCT 2. 12 tCU vs. Ta 0.01 1 0.01 100 0.1 0.1 tCU [s] CCCT [F] 40 0 50 85 0.8 0.6 1.0 1.2 1.4 7525 25 tCU [s] Ta [C]
BATTERY PROTECTION IC FOR 3- SERIAL- OR 4-SERIAL-CELL PACK Rev.5.2_01 S-8254A Series 2. 13 tDL vs. CCDT 2. 14 tDL vs. Ta 0.001 0.1 0.01 0.07 10.1 tDL [s] CCDT [F] 40 0 50 85 100 150 200 25 25 75 tDL [ms] Ta [C] 2. 15 tIOV1 vs. CCDT 2. 16 tIOV1 vs. Ta 0.0001 0.1 0.01 0.001 0.07 10.1 tIOV1 [s] CCDT [F] 40 0 50 85 25 25 75 tIOV1 [ms] Ta [C] 2. 17 tIOV2 vs. Ta 2. 18 tIOV3 vs. Ta 40 0 50 85 0.5 1.0 1.5 2.0 7525 25 tIOV2 [ms] Ta [C] 40 0 50 85 100 200 300 500 400 7525 25 tIOV3 [ms] Ta [C]
BATTERY PROTECTION IC FOR 3-SERIAL- OR 4-SERIAL-CELL PACK S-8254A Series Rev.5.2_01 3. COP / DOP Pin 3. 1 ICOH vs. VCOP 3. 2 ICOL vs. VCOP 0 5 10 15 20 24 0.02 0.03 0.04 0.06 0.07 0.08 0.10 0.05 0.01 0.09 ICOH [A] VCOP [V] 0 7 10.5 14 3.5 ICOL [mA] VCOP [V] 3. 3 IDOH vs. VDOP 3. 4 IDOL vs. VDOP 0 1.8 3.6 5.4 7.2 4.0 5.0 3.5 3.0 2.0 1.5 1.0 2.5 4.5 0.5 IDOH [mA] VDOP [V] 0 3.5 10.5 14 IDOL [mA] VDOP [V]
/X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X55/X4E/X49/X54 /X41/X4E/X47/X4C/X45 /X41/X42/X4C/X49/X43/X20/X49/X6E/X63/X2E /X30/X2E/X31/X37/XB1/X30/X2E/X30/X35 /X39 /X31 /X38 /X31/X36 /X35/X2E/X31/XB1/X30/X2E/X32 /X30/X2E/X32/X32/XB1/X30/X2E/X30/X38/X30/X2E/X36/X35 /X6D/X6D /X4E/X6F/X2E/X20/X46/X54/X30/X31/X36/X2D/X41/X2D/X50/X2D/X53/X44/X2D/X31/X2E/X32 /X46/X54/X30/X31/X36/X2D/X41/X2D/X50/X2D/X53/X44/X2D/X31/X2E/X32 /X54/X53/X53/X4F/X50/X31/X36/X2D/X41/X2D/X50/X4B/X47/X20/X44/X69/X6D/X65/X6E/X73/X69/X6F/X6E/X73
/X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X55/X4E/X49/X54 /X41/X4E/X47/X4C/X45 /X41/X42/X4C/X49/X43/X20/X49/X6E/X63/X2E /X34/X2E/X30/XB1/X30/X2E/X31 /X32/X2E/X30/XB1/X30/X2E/X31 /XF8/X31/X2E/X35/X2B/X30/X2E/X31 /X20/X2D/X30 /XF8/X31/X2E/X36/XB1/X30/X2E/X31 /X38/X2E/X30/XB1/X30/X2E/X31 /X34/X2E/X32/XB1/X30/X2E/X32 /X36/X2E/X35/X2B/X30/X2E/X34 /X20/X2D/X30/X2E/X32 /X30/X2E/X33/XB1/X30/X2E/X30/X35 /X31/X2E/X35/XB1/X30/X2E/X31 /X28/X37/X2E/X32/X29 /X6D/X6D /X38 /X31 /X39 /X31/X36 /X4E/X6F/X2E/X20/X46/X54/X30/X31/X36/X2D/X41/X2D/X43/X2D/X53/X44/X2D/X31/X2E/X31 /X46/X54/X30/X31/X36/X2D/X41/X2D/X43/X2D/X53/X44/X2D/X31/X2E/X31 /X54/X53/X53/X4F/X50/X31/X36/X2D/X41/X2D/X43/X61/X72/X72/X69/X65/X72/X20/X54/X61/X70/X65 /X46/X65/X65/X64/X20/X64/X69/X72/X65/X63/X74/X69/X6F/X6E
/X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X55/X4E/X49/X54 /X41/X4E/X47/X4C/X45 /X41/X42/X4C/X49/X43/X20/X49/X6E/X63/X2E /X31/X37/X2E/X34/XB1/X31/X2E/X30 /X4E/X6F/X2E/X20/X46/X54/X30/X31/X36/X2D/X41/X2D/X52/X2D/X53/X44/X2D/X32/X2E/X30 /X46/X54/X30/X31/X36/X2D/X41/X2D/X52/X2D/X53/X44/X2D/X32/X2E/X30 /X54/X53/X53/X4F/X50/X31/X36/X2D/X41/X2D/X20/X52/X65/X65/X6C /X51/X54/X59/X2E/X32/X2C/X30/X30/X30 /X45/X6E/X6C/X61/X72/X67/X65/X64/X20/X64/X72/X61/X77/X69/X6E/X67/X20/X69/X6E/X20/X74/X68/X65/X20/X63/X65/X6E/X74/X72/X61/X6C/X20/X70/X61/X72/X74 /X32/XB1/X30/X2E/X35 /XF8/X31/X33/XB1/X30/X2E/X32 /XF8/X32/X31/XB1/X30/X2E/X38 /X32/X31/X2E/X34/XB1/X31/X2E/X30 /X31/X37/X2E/X34 /X2B/X32/X2E/X30 /X20/X2D/X31/X2E/X35 /X6D/X6D
/X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X55/X4E/X49/X54 /X41/X4E/X47/X4C/X45 /X41/X42/X4C/X49/X43/X20/X49/X6E/X63/X2E /X6D/X6D /X31/X37/X2E/X34/XB1/X31/X2E/X30 /X4E/X6F/X2E/X20/X46/X54/X30/X31/X36/X2D/X41/X2D/X52/X2D/X53/X31/X2D/X31/X2E/X30 /X46/X54/X30/X31/X36/X2D/X41/X2D/X52/X2D/X53/X31/X2D/X31/X2E/X30 /X54/X53/X53/X4F/X50/X31/X36/X2D/X41/X2D/X20/X52/X65/X65/X6C /X51/X54/X59/X2E/X34/X2C/X30/X30/X30 /X45/X6E/X6C/X61/X72/X67/X65/X64/X20/X64/X72/X61/X77/X69/X6E/X67/X20/X69/X6E/X20/X74/X68/X65/X20/X63/X65/X6E/X74/X72/X61/X6C/X20/X70/X61/X72/X74 /X32/XB1/X30/X2E/X35 /XF8/X31/X33/XB1/X30/X2E/X32 /XF8/X32/X31/XB1/X30/X2E/X38 /X32/X31/X2E/X34/XB1/X31/X2E/X30 /X31/X37/X2E/X34 /X2B/X32/X2E/X30 /X20/X2D/X31/X2E/X35
Disclaimers (Handling Precautions) 1. All the information described herein (product data, specific ations, figures, tables, programs, algorithms and application circuit examples, et c.) is current as of publishing date of this document and is subject to change without notice. 2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. ABLIC Inc. is not liable for any losses, damages, claims or dem ands caused by the reasons other than the products described herein (hereinafter "the products") or infringement o f third-party intellectual property right and any other right due to the use of the information described herein. 3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described herein. 4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute maximum ratings, operation voltage range and electrical characteristics, etc. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to the use of the products outside their specified ranges. 5. Before using the products, co nfirm their applications, and the laws and regulations of the region or country where they are used and verify suitability, safety and other factors for the intended use. 6. When exporting the products, comply with the Foreign Exchang e and Foreign Trade Act and all other export-related laws, and follow the required procedures. 7. The products are strictly prohibited from using, providing o r exporting for the purposes of the development of weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by any provision or export to the person or entity who i ntends to develop, manufacture, use or store nuclear, biological or chemical weapons or missiles, or use any other military purposes. 8. The products are not designed to be used as part of any devi ce or equipment that may affect the human body, human life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment, aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by ABLIC, Inc. Do not apply the products to the above listed devices and equipments. ABLIC Inc. is not liable for any losses, damages, claims or dem ands caused by unauthorized or unspecified use of the products. 9. In general, semiconductor products may fail or malfunction w ith some probability. The user of the products should therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread prevention measures, and malfunction prevention to prevent acci dents causing injury or death, fires and social damage, etc. that may ensue from the products' failure or malfunction. The entire system in which the products are used must be sufficiently evaluated and judged whether the products are allowed to apply for the system on customer's own responsibility. 10. The products are not designed to be radiation-proof. The ne cessary radiation measures should be taken in the product design by the customer depending on the intended use. 11. The products do not affect human health under normal use. H owever, they contain chemical substances and heavy metals and should therefore not be put in the mouth. The fractu re surfaces of wafers and chips may be sharp. Be careful when handling these with the bare hands to prevent injuries, etc. 12. When disposing of t he products, comply with the laws and ordinances of the country or region where they are used. 13. The information described herein contains copyright informa tion and know-how of ABL IC Inc. The information described herein does not convey any license under any intellec tual property rights or any other rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the inf ormation from this document or any part of this document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express permission of ABLIC Inc. 14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales representative. 15. This Disclaimers have been delivered in a text using the Ja panese language, which text, despite any translations into the English language and the Chinese language, shall be controlling. 2.4-2019.07 www.ablic.com