S24C32CH ABLIC | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 38
Technical content
www.ablicinc.com FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM © ABLIC Inc., 2010-2017 Rev.3.0_01_H The S-24C32C/64C H series is a high te mperature operation 2-wire serial E 2PROM for automotive components. The S-24C32C/64C H series has the capacity of 32 K-bit and 64 K-bit, and the organization is 4096 words 8-bit, 8192 words 8-bit, respectively. Page write and sequential read are available. Caution Before using the product in automobile control unit or medical equipment, contact to ABLIC Inc. is indispensable. Features Operating voltage range: Read 2.5 V to 5.5 V Write 2.5 V to 5.5 V Page write: 32 bytes / page Sequential read Operation frequency: 400 kHz (V CC = 2.5 V to 5.5 V) Write time: 5.0 ms max. Noise suppression: Schmitt trigger and noi se filter on input pins (SCL, SDA) Write protect function during the low power supply voltage Endurance: 10 6cycles/word*1 (Ta = 25°C) 3 105cycles/word*1 (Ta = 85°C) 2 105cycles/word*1 (Ta = 105°C) Data retention: 100 years (Ta = 25°C) 30 years (Ta = 85°C) 25 years (Ta = 105°C) Memory capacity: S-24C32C 32 K-bit S-24C64C 64 K-bit Write protect: 100% Initial delivery state: FFh Operation temperature range: Ta = 40°C to 105°C Lead-free (Sn 100%), halogen-free AEC-Q100 qualified*2 *1. For each address (Word: 8-bit) *2. Contact our sales office for details. Packages 8-Pin SOP (JEDEC) 8-Pin TSSOP TMSOP-8 www.ablic.com
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM S-24C32C/64C H Series Rev.3.0_01_H Pin Configurations 1. 8-Pin SOP (JEDEC) Table 1 Top view Figure 1 S-24C32CH-J8T2U3 S-24C64CH-J8T2U3 Pin No Symbol Description
1 A0 Slave address input
2 A1 Slave address input
3 A2 Slave address input
4 GND Ground
5 SDA*1 Serial data I/O
6 SCL*1 Serial clock input
Connected to VCC: Protection valid Open or connected to GND: Protection invalid
8 VCC Power supply
- 8-Pin TSSOP Table 2 Top view Figure 2 S-24C32CH-T8T2U3 S-24C64CH-T8T2U3 Pin No Symbol Description
Connected to VCC: Protection valid Open or connected to GND: Protection invalid
- TMSOP-8 Table 3 Top view Figure 3 S-24C32CH-K8T2U3 S-24C64CH-K8T2U3 Pin No Symbol Description
Connected to VCC: Protection valid Open or connected to GND: Protection invalid *1. Do not use it in high impedance. Remark Refer to the "Package Drawings" for details.
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM Rev.3.0_01_H S-24C32C/64C H Series Block Diagram VCC GND SCL SDA DIN DOUT R / W LOAD INC COMP LOAD WP Start / Stop Detector Serial Clock Controller High-Voltage Generator Voltage Detector Device Address Comparator Address Counter Y Decoder Data Register Memory Cell ArrayX Decoder Selector Data Output ACK Output Controller Figure 4
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM S-24C32C/64C H Series Rev.3.0_01_H AEC-Q100 Qualified This IC supports AEC-Q100 for operation temperature grade 2. Contact our sales office for details of AEC-Q100 reliability specification. Absolute Maximum Ratings Table 4 Item Symbol Absolute Maximum Ratings Unit Power supply voltage V CC 0.3 to 6.5 V Input voltage V IN 0.3 to 6.5 V Output voltage V OUT 0.3 to 6.5 V Operation ambient temperature T opr 40 to 105 °C Storage temperature T stg 65 to 150 °C Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Recommended Operating Conditions Table 5 Item Symbol Condition Ta = 40°C to 105°C Unit Min. Max. Power supply voltage VCC Read 2.5 5.5 V Write 2.5 5.5 V High level input voltage VIH VCC = 2.5 V to 5.5 V 0.7 VCC 5.5 V Low level input voltage VIL VCC = 2.5 V to 5.5 V 0.3 0.3 VCC V Pin Capacitance Table 6 (Ta = 25°C, f = 1.0 MHz, VCC = 5.0 V) Item Symbol Condition Min. Max. Unit Input capacitance C IN VIN = 0 V (SCL, A0, A1, A2, WP) 10 pF I/O capacitance C I / O VI / O = 0 V (SDA) 10 pF Endurance Table 7 Item Symbol Operation Ambient Temperature Min. Max. Unit Endurance N W Ta = 25°C 10 6 cycles / word*1 Ta = 40°C to 85°C 3 105 cycles / word*1 Ta = 40°C to 105°C 2 105 cycles / word*1 *1. For each address (Word: 8 bits) Data Retention Table 8 Item Symbol Operation Ambient Temperature Min. Max. Unit Data retention Ta = 25°C 100 year Ta = 40°C to 85°C 30 year Ta = 40°C to 105°C 25 year
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM Rev.3.0_01_H S-24C32C/64C H Series DC Electrical Characteristics Table 9 Item Symbol Condition Ta = 40°C to 105°C Unit VCC = 2.5 V to 5.5 V fSCL = 400 kHz Min. Max. Current consumption (READ) I CC1 0.8 mA Table 10 Item Symbol Condition Ta = 40°C to 105°C Unit VCC = 2.5 V to 5.5 V fSCL = 400 kHz Min. Max. Current consumption (WRITE) I CC2 4.0 mA Table 11 Item Symbol Condition Ta = 40°C to 105°C Unit VCC = 2.5 V to 5.5 V Min. Max. Standby current consumption I SB V IN = VCC or GND 12.0 A Input leakage current 1 I LI1 SCL, SDA, VIN = GND to VCC 1.2 A Input leakage current 2 I LI2 A0, A1, A2 VIN > 0.7 VCC At standby mode 1.2 A Output leakage current I LO SDA VOUT = GND to VCC 1.2 A Input current 1 I IL WP VIN < 0.3 VCC 50.0 A Input current 2 I IH WP VIN > 0.7 VCC 2.0 A Input Impedance 1 Z IL WP VIN = 0.3 VCC 30 k Input Impedance 2 Z IH WP VIN = 0.7 VCC 500 k Low level output voltage V OL IOL = 3.2 mA 0.4 V IOL = 1.5 mA 0.3 V IOL = 0.7 mA 0.2 V
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM Rev.3.0_01_H S-24C32C/64C H Series Table 14 Item Symbol Ta = 40°C to 105°C Unit VCC = 2.5 V to 5.5 V Min. Max. Write time t WR 5.0 ms SCL SDA D0 Write data Acknowledgment Signal Stop Condition Start ConditiontWR Start Condition WP (valid) WP (invalid) tWS1 tWH1 tWS2 tWH2 Figure 7 Write Cycle Timing
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM S-24C32C/64C H Series Rev.3.0_01_H Pin Functions 1. A0, A1 and A2 (Slave address input) pins In the S-24C32C/64C, to set the slave address, connect each pin of A0, A1, A2 to GND or V CC. Therefore the users can set 8 types of slave address by a combination of A0, A1, A2 pins. Comparing the slave address transmitted from the master device and one that you set, makes possible to select the S-24C32C/64C from other devices connected onto the bus. Each A0, A1 and A2 pin has a pull-down resistor. In open, these pins have the status when they are connected to GND. 2. SDA (Serial data input / output) pin The SDA pin is used for the bi-directional transmission of se rial data. This pin is a signal input pin, and an Nch open drain output pin. In use, generally, connect the SDA line to any other devic e which has the open-drain or open-collector output with Wired-OR connection by pulling up to V CC by a resistor (Figure 8 shows the relation with an output load). 3. SCL (Serial clock input) pin The SCL pin is used for the serial clock input. Since the signals are processed at a ri sing or falling edge of the SCL clock, pay attention to the rising and falling time and comply with the specification. 4. WP (Write protect input) pin The write protect is enabled by connecting the WP pin to V CC. When not using the write pr otect, connect this pin to GND or set in open. Value of load capacity [pF] 100 10 fSCL = 400 kHz Maximum value of pull-up resistor [k] Figure 8 Output Load
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM Rev.3.0_01_H S-24C32C/64C H Series Initial Delivery State Initial delivery state of all addresses is "FFh". Operation 1. Start condition Start is identified by a high to low transition of the SDA line while the SCL line is stable at high. Every operation begins from a start condition. 2. Stop condition Stop is identified by a low to high transition of the SDA line while the SCL line is stable at high. When a device receives a stop condition during a read s equence, the read operation is interrupted, and the device enters standby mode. When a device receives a stop condition during a write sequence, t he reception of the writ e data is halted, and the S-24C32C/64C initiates a write cycle. tSU.STA tHD.STA tSU.STO Start Condition Stop Condition SCL SDA Figure 9 Start / Stop Conditions
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM Rev.3.0_01_H S-24C32C/64C H Series 5. Device addressing To start communication, the master device on the system generates a start condition to the bus line. Next, the master device sends 7-bit device address and a 1-bit read / write instruction code on to the SDA bus. The upper 4 bits of the device address are the “Device Code”, and are fixed to “1010”. In the S-24C32C/64C, successive 3 bits are the “Slave A ddress”. These 3 bits are us ed to identify a device on the system bus and is compared with the pr edetermined value which is defined by t he address input pins (A2, A1, A0). When the comparison result matches, the slave device responds with an acknowlede during the 9th clocks cycle. Slave AddressDevice Code MSB LSB 1 0 1 0 A2 A1 A0 R / W Figure 12 Device Address
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM S-24C32C/64C H Series Rev.3.0_01_H 6. Write 6. 1 Byte write When the master sends a 7-bit device address and a 1-bit read / write instructi on code set to “0”, following a start condition, the S-24C32C/64C acknowledges it. The S-24C32C/64C then receives a upper 8-bit word address and responds with an acknowledge. And t he S-24C32C/64C receives a lower 8-bit word address and responds with an acknowledge. After the S-24C32C/64C receives 8-bit write data and responds with an acknowledge, it receives a stop condition and that initiates the write cycle at the addressed memory. During the write cycle all operations are forbidden and no acknowledge is generated. A2 A1 A0 S T A R T 1 0 1 0 W R I T E DEVICE ADDRESS UPPER WORD ADDRESS R W M S B SDA LINE A C K L S B LOWER WORD ADDRESS S T O PDATA X W7 W6 W5 W4 W3 W2 W1 W0 D7 D6 D5 D4 D3 D2 D1 D0W12 W11 W10 W9 W8 A C K A C K X A C K X Remark W12 is arbitrary in the S-24C32C. Figure 13 Byte Write
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM Rev.3.0_01_H S-24C32C/64C H Series 6. 2 Page write The page write mode allows up to 32 bytes to be written in a single write operation in the S-24C32C/64C. Its basic process to transmit data is as same as byte write, but it operat es page write by sequentially receiving 8-bit write data as much data as the page size has. When the S-24C32C/64C receives a 7-bit device address and a 1-bit read / write instruction code set to “0”, following a start condition, it generates an acknowledge. And the S-24C32C/64C receives a upper 8-bit word address, and responds with an acknowl edge. Then the S-24C32C/64C receives a lower 8-bit word address, and responds with an acknowledge. After the S-24C32C/64C receives 8-bit write data and responds with an acknowledge, it receives 8-bit write data corresponding to the next word address, and generates an acknowledge. The S-24C32C/64C repeats reception of 8-bit write data and generation of acknowledge in succession. The S-24C32C/64C can receive as many write data as the maximum page size. Receiving a stop condition initiates a write cycle of the area starting from the designated memory address and having the page size equal to the received write data. A2 A1 A0 S T A R T 1 0 1 0 W R I T E DEVICE ADDRESS UPPER WORD ADDRESS (n) R W M S B SDA LINE A C K L S B LOWER WORD ADDRESS (n)
0 X W7 W6 W5 W4 W3 W2 W1 W0
DATA (n) D7 D0 S T O P W12 W11 W10 W9 W8 A C K X A C K DATA (n+x) D7 D0X Remark W12 is arbitrary in the S-24C32C. Figure 14 Page Write In the S-24C32C, the lower 5 bits of the word address are automatically increment ed every time when the S-24C32C/64C receives 8-bit write data. If the size of the write data exceeds 32 bytes, the upper 7 bits of the word address remain unchanged, and the lower 5 bits are rolled over and the last 32-byte data that the S-24C32C received will be overwritten. In the S-24C64C, the lower 5 bits of the word address are automatically increment ed every time when the S-24C32C/64C receives 8-bit write data. If the size of the write data exceeds 32 bytes, the upper 8 bits of the word address remain unchanged, and the lower 5 bits are rolled over and the last 32-byte data that the S-24C64C received will be overwritten.
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM S-24C32C/64C H Series Rev.3.0_01_H 6. 3 Write protect Write protect is available in the S-24C32C/ 64C. When the WP pin is connected to the V CC, write operation to memory area is inhibited. When the WP pin is connected to GND or set in open, the write protect is invalid, and write operation in all memory area is available. Fix the level of the WP pin from start condition in the write operation (byte write, page write) until stop condition. If the WP pin changes during this time, the address data being written at this time is not guaranteed. Regarding the timing of write protect, refer to Figure 7. In not using the write protect, connect t he WP pin to GND or set it open. The wr ite protect is valid in the range of operation power supply voltage. As seen in Figure 15 when the write protect is valid, the S- 24C32C/64C does not gener ate an acknowledgment signal after data input. A2 A1 A0 S T A R T 1 0 1 0 W R I T E DEVICE ADDRESS UPPER WORD ADDRESS R W M S B SDA LINE A C K L S B LOWER WORD ADDRESS S T O PDATA X W7 W6 W5 W4 W3 W2 W1 W0 D7 D6 D5 D4 D3 D2 D1 D0W12 W11 W10 W9 W8 A C K N A C K X A C K WP X Remark W12 is arbitrary in the S-24C32C. Figure 15 Write Protect
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM Rev.3.0_01_H S-24C32C/64C H Series 6. 4 Acknowledge polling Acknowledge polling is used to know the completion of the write cycle in the S-24C32C/64C. After the S-24C32C/64C receives a stop condition and once starts the write cycle, all operations are inhibited and no response is made to the signal transmitted by the master device. Accordingly the master device can recognize the completi on of the write cycle in t he S-24C32C/64C by detecting a response from the slave device after transmitting the start condition, the device address and the read / write instruction code to the S-24C32C/64C (slave device). That is, if the S-24C32C/64C does not generate an acknowledgment signal, the write cycle is in progress and if the S-24C32C/64C generates an acknowledgment signal, the write cycle has been completed. It is recommended to use the read instru ction “1” as the read / write instru ction code transmitted by the master device. S T A R T A C K N A C K Remark Users are able to input word address and data afte r ACK output in acknowledge polling during write. Users are able to read data after ACK output in acknowledge polling during read. However, after that users input the write instruction, a start condition may not be input during data output. Input a stop condition and the next instruction after data output and ACK output. SDA LINE DEVICE ADDRESS DATA D2 D1 D0 S T O P tWR S T A R T S T A R T A C K SDA LINE DATA D2 D1 D0 S T O P tWR S T A R T N A C K S T O P DATA NO ACK from Master Device R E A D R W W R I T E R W
0 DEVICE
W R I T E R W 0DEVICE ADDRESS DEVICE ADDRESS R E A D R W Acknowledge polling during write Acknowledge polling during read A C K S T A R T DEVICE ADDRESS R W A C K WORD ADDRESS Figure 16 Usage Example of Acknowledge Polling
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM S-24C32C/64C H Series Rev.3.0_01_H 7. Read 7. 1 Current address read Either in writing or in reading t he S-24C32C/64C holds the last access ed memory address. The memory address is maintained as long as the power voltage does not decrease less than the operating voltage. The master device can read t he data at the memory address of the curr ent address pointer without assigning the word address as a result, when it recognizes the positi on of the address pointer in the S-24C32C/64C. This is called “Current Address Read”. In the following the address counter in the S-24C32C/64C is assumed to be “n”. When the S-24C32C/64C receives a 7-bit device address and a 1-bit read / write instruction code set to “1” following a start condition, it responds with an acknowledge. Next, an 8-bit data at the address “n” is sent from the S-24C32C/64C synchronous to the SCL clock. The address counter is incremented and the content of the address counter becomes n1. The master device outputs stop condition not an acknowledge, the reading of S-24C32C/64C is ended. S T A R T 1 0 1 0 R E A D S T O P DEVICE ADDRESS R W M S B SDA LINE A2 A1 A0 D7 D6 D5 D4 D3 D2 D1D0 A C K L S B DATA NO ACK from Master Device Figure 17 Current Address Read Attention should be paid to the following point on the recognition of the address pointer in the S-24C32C/64C. In Read, the memory address counter in the S-24C32C/64C is automatically incremented after output of the 8th bit of the data. In Write, on the other hand, the upper bits of the memory addre ss (the upper bits of the word address*1) are left unchanged and are not incremented. *1. In the S-24C32C, the upper 7 bits of the word address. In the S-24C64C, the upper 8 bits of the word address.
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM Rev.3.0_01_H S-24C32C/64C H Series 7. 2 Random read Random read is used to read the data at an arbitrary memory address. A dummy write is performed to load the memory address into the address counter. When the S-24C32C/64C receives a 7-bit device address and a 1-bit read / write instruction code set to “0” following a start condition, it responds with an acknowledge. The S-24C32C/64C then receives a upper 8-bit word address and responds with an acknowledge. And the S-24C32C/64C receives a lower 8-bit word address and responds with an acknowledge. The memory address is loaded to the address counter in the S- 24C32C/64C by these operations. Reception of write data does not follow in a dummy write whereas reception of write data follows in byte write and in page write. Since the memory address is loaded into the memory addr ess counter by dummy writ e, the master device can read the data starting from the arbitrary memory address by transmitting a new start condition and performing the same operation in the current address read. That is, when the S-24C32C/64C receiv es a 7-bit device address and a 1-bit r ead / write instruction code set to “1”, following a start condition signal, it responds with an acknowledge. Next, 8-bit dat a is transmitted from the S-24C32C/64C in synchronous to the SCL clock. The master device outputs stop c ondition not an acknowledge, the reading of S-24C32C/64C is ended. SDA LINE S T A R T 1 0 1 0 W R I T E DEVICE ADDRESS LOWER WORD ADDRESS R W M S B A2 A1 A0 A C K L S B W7 W6 W5 W4 W3 W2 W1 A C K DUMMY WRITE S T O P S T A R T 1 0 1 0 R E A D DEVICE ADDRESS R W M S B A2 A1 A0 A C K L S B 1 下図へ続く NO ACK from Master Device DATA UPPER WORD ADDRESS X W9W8X D7 D6 D5D4D3D2D1D0 A C K W11 W10 W0X X W12 Remark W12 is arbitrary in the S-24C32C. Figure 18 Random Read
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM S-24C32C/64C H Series Rev.3.0_01_H 7. 3 Sequential read When the S-24C32C/64C receives a 7-bit device address and a 1-bit read / write instruction code set to “1” following a start condition both in current address read and random read, it responds with an acknowledge. When an 8-bit data is output from t he S-24C32C/64C synchronous to the SC L clock, the address counter is automatically incremented. When the master device responds with an acknowledge, the dat a at the next memory address is transmitted. Response with an acknowledge by the master device has the memory address count er in the S-24C32C/64C incremented and makes it possible to read data in succession. This is called “Sequential Read”. The master device outputs stop condition not an acknowledge, the reading of S-24C32C/64C is ended. Data can be read in succession in the sequential read mode. When the memory address counter reaches the last word address, it rolls over to the first word address. R E A D S T O P DEVICE ADDRESS R W A C K A C K A C K A C K SDA LINE DATA (n) D7 D0 D7 D0D7 D0 D7 D0 DATA (n+1) DATA (n+2) DATA (n+x) NO ACK from Master Device Figure 19 Sequential Read
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM Rev.3.0_01_H S-24C32C/64C H Series Write Protect Function during the Low Power Supply Voltage The S-24C32C/64C has a built-in detection circuit which operates with the low power supply voltage, cancels Write when the power supply voltage drops and power-on. Its detection and release voltages are 1.20 V typ. (Refer to Figure 20). The S-24C32C/64C cancels Write by detecting a low power supply voltage when it receives a stop condition. In the data trasmission and the Write operation, data in the address written during the low power supply voltage is not assurable. Release Voltage (VDET) 1.20 V Typ. Power Supply Voltage Detection Voltage (VDET) 1.20 V Typ. Write Instruction cancel Figure 20 Operation during Low Power Supply Voltage
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM S-24C32C/64C H Series Rev.3.0_01_H 3. Phase adjustment during S-24C32C/64C access The S-24C32C/64C does not have a pin to reset (the internal ci rcuit). The users cannot forcibly reset it externally. If the communication to the S-24C32C/64C interrupted, the users need to handle it as you do for software. In the S-24C32C/64C, users are able to reset the internal circuit by inputting a start condition and a stop condition. Although the reset signal is input to the master device, the S-24C32C/64C’s internal circuit does not go in reset, but it does by inputting a stop condition to the S-24C32C/64C. T he S-24C32C/64C keeps the sa me status thus cannot do the next operation. Especially, this case corresponds to t hat only the master device is reset when the power supply voltage drops. If the power supply voltage restored in th is status, input the instruction afte r resetting (adjusting the phase with the master device) the S-24C32C/64C. How to reset is shown below. [How to reset S-24C32C/64C] The S-24C32C/64C is able to be reset by a start and stop instructions. When the S-24C32C/64C is reading data “0” or is outputting the acknowledgment signal , outputs “0” to the SDA line. In th is status, the ma ster device cannot output an instruction to the SDA line. In this case, terminate the acknow ledgment output operat ion or the Read operation, and then input a start instruction. Figure 25 shows this procedure. First, input a start condition. Then transmit 9 clocks (dummy clock) of SCL. During this time, the master device sets the SDA line to “H”. By this operation, the S-24C32C/64C in terrupts the acknowledgment output operation or data output, so input a start condition *1. When a start condition is input, the S-24C32C/64C is reset. To make doubly sure, input the stop condition to the S-24C32C/64C. The normal operation is then possible. 1 2 8 9 SCL SDA Start Condition Stop Condition Start ConditionDummy Clock Figure 25 Resetting S-24C32C/64C *1. After 9 clocks (dummy clock), if the SCL clock conti nues to being output without i nputting a start condition, S-24C32C/64C may go in the write operat ion when it receives a stop condition. To prevent this, input a start condition after 9 clocks (dummy clock). Remark Regarding this reset procedure with dummy clo ck, it is recommended to perform at the system initialization after applying the power supply voltage.
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM Rev.3.0_01_H S-24C32C/64C H Series 4. Acknowledge check The I2C-bus protocol includes an acknow ledge check function as a handshake f unction to prevent a communication error. This function allows detection of a communica tion failure during data comm unication between the master device and S-24C32C/64C. This function is effective to prevent malfunction, so it is recommended to perform an acknowledge check with the master device. 5. Built-in power-on-clear circuit The S-24C32C/64C has a built-in power-on- clear circuit that initializes itself at the same time during power-on. Unsuccessful initialization may cause a malfunction. To operate the power-on-clear circuit normally, the following conditions must be satisfied to raise the power supply voltage. 5. 1 Raising power supply voltage Shown in Figure 26, raise the power supply voltage from 0.2 V max., within the time defined as t RISE which is the time required to reach the power supply voltage to be set. For example, if the power supply voltage is 5.0 V, t RISE = 200 ms seen in Figure 27. The power supply voltage must be raised within 200 ms. 0.2 V VINIT (Max.) tINIT *2 (Max.) tRISE (Max.) Power Supply Voltage (V CC)
0 V*1
*1. 0 V means there is no difference in potential between the VCC pin and the GND pin of the S-24C32C/64C. *2. tINIT is the time required to initialize the S-24C32C/64C. No instructions are accepted during this time. Figure 26 Raising Power Supply Voltage
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM S-24C32C/64C H Series Rev.3.0_01_H Power Supply Voltage Rise Time (t RISE) Max. [ms] Power Supply Voltage (V CC) [V] 5.0 4.0 3.0 2.0 100 150 200 For example: If the supply voltage = 5.0 V, raise the power supply voltage to 5.0 V within 200 ms. Figure 27 Power Supply Voltage Rise Time When initialization is successfully completed by the pow er-on-clear circuit, the S-24C32C/64C enters the standby status. If the power-on-clear circuit does not operate; The S-24C32C/64C has not completed init ialization, an instruction previously input is still valid or an instruction may be inappropriately recognized. In this case, S-24C32C/64C may perform the Write operation. The voltage drops due to power off while the S-24C32C/64C is being accessed. Even if the master device is reset due to the low power voltage, the S-24C32C/64C may malfunction unless the power-on-clear operation conditions of S-24C32C/64C are satisfied. When not keeping to the power supply voltage rise time seen in Figure 27, adjust the phase (reset) to reset the internal circuit in the S-24C32C/64C normally.
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM Rev.3.0_01_H S-24C32C/64C H Series 8. Operation when input stop condition during input write data The S-24C32C/64C does the wr ite operation only when it re ceives data of 1 byte or more and receives a stop condition immediately after ACK output. Refer to Figure 31 regarding details. R W S T A R T 1 0 1 0 W R I T E S T O PDEVICE ADDRESS DATA (n) LOWER WORD ADDRESS (n) M S B SDA LINE A2 A1 A0 A C K L S B A C K A C K
0 W7 W0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D0
A C K A C K DATA (n+1) DATA (n+x) Write Inhibition by stop condition Write Inhibition by stop condition UPPER WORD ADDRESS (n) A C K x x W12 W8 Write Inhibition by stop condition Write Enable by stop condition Write Enable by stop condition x Remark W12 is arbitrary in the S-24C32C. Figure 31 Write Operation by Inputting Stop Condition during Write 9. Command cancel by start condition By a start condition, users are able to cancel command wh ich is being input. However, adjust the phase while the S-24C32C/64C is outputting “L” because users are not able to input a star t condition. When users cancel the command, there may be a case that t he address will not be identified. Use r andom read for the r ead operation, not current address read. 10. Precaution for use Do not operate these ICs in excess of the absolute maximum ratings. Attent ion should be paid to the power supply voltage, especially. The surge volt age which exceeds the maximum absol ute ratings can cause latch-up and malfunction. Perform operations after confirming the detailed operation condition in the data sheet. Operations with moisture on the S-24C32C/64C pins may occur malfunction by short-circuit between pins. Especially, in occasions like picking the S-24C32C/64C up from low tem perature tank during the evaluation. Be sure that not remain frost on the S-24C32C/64C’s pins to prevent malfunction by short-circuit. Also attention should be paid in using on environment, which is easy to dew for the same reason.
FOR AUTOMOTIVE 105°C OPERATION 2-WIRE SERIAL E2PROM S-24C32C/64C H Series Rev.3.0_01_H Precaution
- Do not apply an electrostatic discharge to this IC that ex ceeds the performance ratings of the built-in electrostatic protection circuit.
- ABLIC Inc. claims no responsibility for any and all disputes ar ising out of or in connection with any infringement of the products including this IC upon patents owned by a third party. Product Name Structure 1. Product name S-24CxxC H - xxxx U 3 Product name S-24C32C : 32 K-bit S-24C64C : 64 K-bit Fixed Package name (abbreviation) and IC packing specification J8T2: 8-Pin SOP (JEDEC), Tape T8T2: 8-Pin TSSOP, Tape K8T2: TMSOP-8, Tape Environmental code U: Lead-free (Sn 100%), halogen-free Remark Please contact our sales office for products with product name structure ot her than those specified above. 2. Package Package Name Drawing Code Package Tape Reel 8-Pin SOP (JEDEC) FJ008-A-P-SD FJ008-D-C-SD FJ008-D-R-S1 8-Pin TSSOP FT008-A-P-SD FT008-E-C-SD FT008-E-R-S1 TMSOP-8 FM008-A-P-SD FM008-A-C-SD FM008-A-R-SD
/X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X55/X4E/X49/X54 /X41/X4E/X47/X4C/X45 /X41/X42/X4C/X49/X43/X20/X49/X6E/X63/X2E /X4E/X6F/X2E/X20/X46/X4A/X30/X30/X38/X2D/X41/X2D/X50/X2D/X53/X44/X2D/X32/X2E/X32 /X6D/X6D /X53/X4F/X50/X38/X4A/X2D/X44/X2D/X50/X4B/X47/X20/X44/X69/X6D/X65/X6E/X73/X69/X6F/X6E/X73 /X46/X4A/X30/X30/X38/X2D/X41/X2D/X50/X2D/X53/X44/X2D/X32/X2E/X32 /X30/X2E/X34/XB1/X30/X2E/X30/X35/X31/X2E/X32/X37 /X30/X2E/X32/X30/XB1/X30/X2E/X30/X35 /X35/X2E/X30/X32/XB1/X30/X2E/X32 /X31 /X34 /X38/X35
/X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X55/X4E/X49/X54 /X41/X4E/X47/X4C/X45 /X41/X42/X4C/X49/X43/X20/X49/X6E/X63/X2E /X6D/X6D /X35 /X38/X31 /X34 /XF8/X32/X2E/X30/XB1/X30/X2E/X30/X35 /XF8/X31/X2E/X35/X35/XB1/X30/X2E/X30/X35 /X30/X2E/X33/XB1/X30/X2E/X30/X35 /X32/X2E/X31/XB1/X30/X2E/X31/X38/X2E/X30/XB1/X30/X2E/X31 /X36/X2E/X37/XB1/X30/X2E/X31 /X32/X2E/X30/XB1/X30/X2E/X30/X35 /X46/X65/X65/X64/X20/X64/X69/X72/X65/X63/X74/X69/X6F/X6E /X34/X2E/X30/XB1/X30/X2E/X31/X28/X31/X30/X20/X70/X69/X74/X63/X68/X65/X73/X3A/X34/X30/X2E/X30/XB1/X30/X2E/X32/X29 /X53/X4F/X50/X38/X4A/X2D/X44/X2D/X43/X61/X72/X72/X69/X65/X72/X20/X54/X61/X70/X65 /X4E/X6F/X2E/X20/X46/X4A/X30/X30/X38/X2D/X44/X2D/X43/X2D/X53/X44/X2D/X31/X2E/X31 /X46/X4A/X30/X30/X38/X2D/X44/X2D/X43/X2D/X53/X44/X2D/X31/X2E/X31
/X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X55/X4E/X49/X54 /X41/X4E/X47/X4C/X45 /X41/X42/X4C/X49/X43/X20/X49/X6E/X63/X2E /X6D/X6D /X51/X54/X59/X2E/X34/X2C/X30/X30/X30 /X32/XB1/X30/X2E/X35 /X31/X33/X2E/X35/XB1/X30/X2E/X35 /X36/X30/XB0 /X32/XB1/X30/X2E/X35 /XF8/X31/X33/XB1/X30/X2E/X32 /XF8/X32/X31/XB1/X30/X2E/X38 /X45/X6E/X6C/X61/X72/X67/X65/X64/X20/X64/X72/X61/X77/X69/X6E/X67/X20/X69/X6E/X20/X74/X68/X65/X20/X63/X65/X6E/X74/X72/X61/X6C/X20/X70/X61/X72/X74 /X53/X4F/X50/X38/X4A/X2D/X44/X2D/X52/X65/X65/X6C /X4E/X6F/X2E/X20/X46/X4A/X30/X30/X38/X2D/X44/X2D/X52/X2D/X53/X31/X2D/X31/X2E/X30 /X46/X4A/X30/X30/X38/X2D/X44/X2D/X52/X2D/X53/X31/X2D/X31/X2E/X30
/X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X55/X4E/X49/X54 /X41/X4E/X47/X4C/X45 /X41/X42/X4C/X49/X43/X20/X49/X6E/X63/X2E /X54/X53/X53/X4F/X50/X38/X2D/X45/X2D/X50/X4B/X47/X20/X44/X69/X6D/X65/X6E/X73/X69/X6F/X6E/X73 /X4E/X6F/X2E/X20/X46/X54/X30/X30/X38/X2D/X41/X2D/X50/X2D/X53/X44/X2D/X31/X2E/X32 /X46/X54/X30/X30/X38/X2D/X41/X2D/X50/X2D/X53/X44/X2D/X31/X2E/X32 /X30/X2E/X31/X37/XB1/X30/X2E/X30/X35 /X33/X2E/X30/X30/X2B/X30/X2E/X33 /X20/X2D/X30/X2E/X32 /X30/X2E/X36/X35 /X30/X2E/X32/XB1/X30/X2E/X31 /X31 /X34 /X35/X38 /X6D/X6D
/X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X55/X4E/X49/X54 /X41/X4E/X47/X4C/X45 /X41/X42/X4C/X49/X43/X20/X49/X6E/X63/X2E /XF8/X31/X2E/X35/X35/XB1/X30/X2E/X30/X35 /X32/X2E/X30/XB1/X30/X2E/X30/X35 /X38/X2E/X30/XB1/X30/X2E/X31/XF8/X31/X2E/X35/X35/X2B/X30/X2E/X31 /X20/X2D/X30/X2E/X30/X35 /X28/X34/X2E/X34/X29 /X30/X2E/X33/XB1/X30/X2E/X30/X35 /X31 /X34 /X35 /X38 /X34/X2E/X30/XB1/X30/X2E/X31 /X46/X65/X65/X64/X20/X64/X69/X72/X65/X63/X74/X69/X6F/X6E /X54/X53/X53/X4F/X50/X38/X2D/X45/X2D/X43/X61/X72/X72/X69/X65/X72/X20/X54/X61/X70/X65 /X4E/X6F/X2E/X20/X46/X54/X30/X30/X38/X2D/X45/X2D/X43/X2D/X53/X44/X2D/X31/X2E/X30 /X46/X54/X30/X30/X38/X2D/X45/X2D/X43/X2D/X53/X44/X2D/X31/X2E/X30 /X2B/X30/X2E/X34 /X20/X2D/X30/X2E/X32/X36/X2E/X36 /X6D/X6D
/X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X55/X4E/X49/X54 /X41/X4E/X47/X4C/X45 /X41/X42/X4C/X49/X43/X20/X49/X6E/X63/X2E /X45/X6E/X6C/X61/X72/X67/X65/X64/X20/X64/X72/X61/X77/X69/X6E/X67/X20/X69/X6E/X20/X74/X68/X65/X20/X63/X65/X6E/X74/X72/X61/X6C/X20/X70/X61/X72/X74 /X32/XB1/X30/X2E/X35 /XF8/X31/X33/XB1/X30/X2E/X35 /XF8/X32/X31/XB1/X30/X2E/X38 /X31/X33/X2E/X34/XB1/X31/X2E/X30 /X31/X37/X2E/X35/XB1/X31/X2E/X30 /X34/X2C/X30/X30/X30/X51/X54/X59/X2E /X54/X53/X53/X4F/X50/X38/X2D/X45/X2D/X52/X65/X65/X6C /X46/X54/X30/X30/X38/X2D/X45/X2D/X52/X2D/X53/X31/X2D/X31/X2E/X30 /X6D/X6D /X4E/X6F/X2E/X20/X46/X54/X30/X30/X38/X2D/X45/X2D/X52/X2D/X53/X31/X2D/X31/X2E/X30
/X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X55/X4E/X49/X54 /X41/X4E/X47/X4C/X45 /X41/X42/X4C/X49/X43/X20/X49/X6E/X63/X2E /X32/X2E/X39/X30/XB1/X30/X2E/X32 /X38/X35 /X30/X2E/X32/XB1/X30/X2E/X31 /X30/X2E/X36/X35/XB1/X30/X2E/X31 /X30/X2E/X31/X33/XB1/X30/X2E/X31 /X31/X34 /X54/X4D/X53/X4F/X50/X38/X2D/X41/X2D/X50/X4B/X47/X20/X44/X69/X6D/X65/X6E/X73/X69/X6F/X6E/X73 /X4E/X6F/X2E/X20/X46/X4D/X30/X30/X38/X2D/X41/X2D/X50/X2D/X53/X44/X2D/X31/X2E/X32 /X46/X4D/X30/X30/X38/X2D/X41/X2D/X50/X2D/X53/X44/X2D/X31/X2E/X32 /X6D/X6D
/X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X55/X4E/X49/X54 /X41/X4E/X47/X4C/X45 /X41/X42/X4C/X49/X43/X20/X49/X6E/X63/X2E /X30/X2E/X33/X30/XB1/X30/X2E/X30/X35 /X31/X2E/X30/X30/XB1/X30/X2E/X31 /X31/X2E/X30/X35/XB1/X30/X2E/X30/X35 /X31/X2E/X35 /X32/X2E/X30/X30/XB1/X30/X2E/X30/X35 /X34/X2E/X30/X30/XB1/X30/X2E/X31 /X33/X2E/X32/X35/XB1/X30/X2E/X30/X35 /X34/X2E/X30/X30/XB1/X30/X2E/X31 /X31/X34 /X35/X38 /X54/X4D/X53/X4F/X50/X38/X2D/X41/X2D/X43/X61/X72/X72/X69/X65/X72/X20/X54/X61/X70/X65 /X46/X65/X65/X64/X20/X64/X69/X72/X65/X63/X74/X69/X6F/X6E /X4E/X6F/X2E/X20/X46/X4D/X30/X30/X38/X2D/X41/X2D/X43/X2D/X53/X44/X2D/X32/X2E/X30 /X46/X4D/X30/X30/X38/X2D/X41/X2D/X43/X2D/X53/X44/X2D/X32/X2E/X30 /X2B/X30/X2E/X31 /X20/X2D/X30 /X6D/X6D
/X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X55/X4E/X49/X54 /X41/X4E/X47/X4C/X45 /X41/X42/X4C/X49/X43/X20/X49/X6E/X63/X2E /X31/X36/X2E/X35/X6D/X61/X78/X2E /X31/X33/X2E/X30/XB1/X30/X2E/X33 /X51/X54/X59/X2E/X34/X2C/X30/X30/X30 /X28/X36/X30/XB0/X29/X28/X36/X30/XB0/X29 /X31/X33/XB1/X30/X2E/X32 /X45/X6E/X6C/X61/X72/X67/X65/X64/X20/X64/X72/X61/X77/X69/X6E/X67/X20/X69/X6E/X20/X74/X68/X65/X20/X63/X65/X6E/X74/X72/X61/X6C/X20/X70/X61/X72/X74 /X54/X4D/X53/X4F/X50/X38/X2D/X41/X2D/X52/X65/X65/X6C /X4E/X6F/X2E/X20/X46/X4D/X30/X30/X38/X2D/X41/X2D/X52/X2D/X53/X44/X2D/X31/X2E/X30 /X46/X4D/X30/X30/X38/X2D/X41/X2D/X52/X2D/X53/X44/X2D/X31/X2E/X30 /X6D/X6D
Disclaimers (Handling Precautions) 1. All the information described herein (product data, specific ations, figures, tables, programs, algorithms and application circuit examples, et c.) is current as of publishing date of this document and is subject to change without notice. 2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. ABLIC Inc. is not liable for any losses, damages, claims or dem ands caused by the reasons other than the products described herein (hereinafter "the products") or infringement o f third-party intellectual property right and any other right due to the use of the information described herein. 3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described herein. 4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute maximum ratings, operation voltage range and electrical characteristics, etc. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to the use of the products outside their specified ranges. 5. Before using the products, co nfirm their applications, and the laws and regulations of the region or country where they are used and verify suitability, safety and other factors for the intended use. 6. When exporting the products, comply with the Foreign Exchang e and Foreign Trade Act and all other export-related laws, and follow the required procedures. 7. The products are strictly prohibited from using, providing o r exporting for the purposes of the development of weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by any provision or export to the person or entity who i ntends to develop, manufacture, use or store nuclear, biological or chemical weapons or missiles, or use any other military purposes. 8. The products are not designed to be used as part of any devi ce or equipment that may affect the human body, human life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment, aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by ABLIC, Inc. Do not apply the products to the above listed devices and equipments. ABLIC Inc. is not liable for any losses, damages, claims or dem ands caused by unauthorized or unspecified use of the products. 9. In general, semiconductor products may fail or malfunction w ith some probability. The user of the products should therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread prevention measures, and malfunction prevention to prevent acci dents causing injury or death, fires and social damage, etc. that may ensue from the products' failure or malfunction. The entire system in which the products are used must be sufficiently evaluated and judged whether the products are allowed to apply for the system on customer's own responsibility. 10. The products are not designed to be radiation-proof. The ne cessary radiation measures should be taken in the product design by the customer depending on the intended use. 11. The products do not affect human health under normal use. H owever, they contain chemical substances and heavy metals and should therefore not be put in the mouth. The fractu re surfaces of wafers and chips may be sharp. Be careful when handling these with the bare hands to prevent injuries, etc. 12. When disposing of t he products, comply with the laws and ordinances of the country or region where they are used. 13. The information described herein contains copyright informa tion and know-how of ABL IC Inc. The information described herein does not convey any license under any intellec tual property rights or any other rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the inf ormation from this document or any part of this document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express permission of ABLIC Inc. 14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales representative. 15. This Disclaimers have been delivered in a text using the Ja panese language, which text, despite any translations into the English language and the Chinese language, shall be controlling. 2.4-2019.07 www.ablic.com