PS12

PS12 SUTEX | Alldatasheet

Document overview

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Technical content

Features

Power supply sequencer with four outputs Power-up and power-down sequencing Six programmable delays Maximum 90V supply voltage Input voltage window comparator Low power supply current (500µA typical) 16-Lead SOIC Package

Applications

Reduction of transient current demand and protection of sensitive loads Telecom and networking systems High voltage MEMS and display driver supplies General Description Many systems require that their power supplies are enabled and disabled sequentially in order to reduce transient current demand on the power bus, or to avoid damage to components having multiple supply voltages such as microprocessors, ASICs, MEMS drivers, etc. The PS12 incorporates a power-up delay timer, a window voltage comparator, 4 open drain enable outputs, and 6 enable delay timers. The enable delays are individually programmable for both the power-up (ABCD) and the power- down (DCBA) sequence. Power-up and power-down are controlled by a window comparator formed by the ON and OV voltage comparators. V IN voltage within the window initiates power-up; V IN voltage outside of the window maintains or initiates power-down. The power-up sequence may be interrupted while in progress. The power-down sequence, once initiated, cannot be interrupted until it is brought to completion. Typical Application Circuit Quad Power Sequencing Controller ENA 11 +12V RDC RCB RBA CPUD OUT OUTENA 12 OUTENA 13 OUTENA 14 RAB RBC RCD +5V CONVERTER +3.3V CONVERTER +1.8V CONVERTER +12V CONVERTER PS12NG TCB TBA PUD PSD PSC PSB PSA TDC OV ON TBC TCDTAB VIN VEE

Ordering Information

-G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Parameter Value VIN1 -0.3V...+100V ON, OV1 -0.3V...+8V ESD (all pins except VIN, PSA...PSD)2 ±2kV Operating ambient temperature -40 OC...+85OC Operating junction temperature -40 OC...+125OC Storage temperature -65 OC...+150OC Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Notes: 1. Referenced to VEE 2. HBM, 1.5kΩ, 100pF Block Diagram Thermal Resistance Package θja 16-Lead SOIC 65K/W to 120K/W (PCB Layout dependent) VIN RAB TBC RBC TCD RCD 1.20 V CPUD PUD PD 1.20V PU 1.00V INTERNAL VOLTAGE REGULATOR CONTROL LOGIC TAB OV ON PS12 12µA PU 1.20V PD 1.00V RDC TCB RCB TBA RBA TDC PSD PSC PSB PSA VEE Pin Confi guration NC VIN PSD PSC PSB PSA TBA VEE PUD ON OV TAB TBC TCD 8 9TDC TCB 16-Lead SOIC (top view) Pin Confi guration Y = Last Digit of Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin A = Assembler ID* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking PS12NG YWW LLLLLLLL CCCCCCCCC AAA

Symbol Parameter Min Typ Max Units Conditions Supply (VIN) VVIN Supply voltage 4.5 - 90 V * --- IVIN Supply current - 500 625 µA -V IN = 36V, RT = 2MΩ - 400 - - V IN = 12V, RT = 2MΩ Input Voltage Monitor (ON) VONPU Power-up threshold 1.16 1.22 1.28 V * V ON Rising VONPD Power-down threshold 1.06 1.12 1.18 V * V ON Falling VHY Power-up/Power-down hysteresis - 100 - mV - --- ION Input Current - ±1 - nA - --- Input Voltage Monitor (OV) VOVPD Power-down threshold 1.16 1.22 1.28 V * V OV Rising VOVPU Power-up threshold 1.06 1.12 1.18 V * V OV Falling VHY Power-up/power-down hysteresis - 100 - mV - --- IOV Input current - ±1 - nA - --- Power Supply Enable Outputs (PSA, PSB, PSC, PSD) ILKG High state leakage current - - 10 µA * V PS = 90V PS = HiZ VSAT Low state output voltage - - 100 mV - I PS = 1mA PS = Low Power-up Delay (PUD) IPUD Output current -8.4 -12 -16 µA - --- VPUD Threshold voltage 1.15 1.20 1.25 V - --- RDISCH Discharge FET ON resistance - 500 - Ω - I DISCH = 1mA Power Supply Enable Timing (TAB, TBC, TCD, TDC, TCB, TBA) RT Timing resistance range 50 - 2000 kΩ - --- TPSPS(MAX) Maximum PS-to-PS delay 160 200 240 ms - R T = 2MΩ TPSPS(MIN) Minimum PS-to-PS delay 4.0 5.0 6.0 ms - R T = 50kΩ

Electrical Characteristics

Pin # Function Description 15 VIN Power supply pins. VIN positive with respect to VEE. The outputs PSA thru PSD are pulled to a logic low state upon application of power.1 VEE 2P U D Hookup pin for the power-up-delay (PUD) timing capacitor. Pin pulls capacitor to ground upon application of power. (See timing diagram) 3 ON Input pin of the ON comparator. Rising transition initiates power-up sequence. 4 OV Input pin of the OV comparator. Rising transition initiates the power-down sequence. 5T A B Hookup pins for timing resistors. On power-up, the resistor at TAB determines the delay between the rising transitions of PSA and PSB; similarly, TBC relates to ( PSB / PSC ), and TCD to ( PSC / PSD ). On power-down, the resistor at TDC determines the delay between the falling transitions of PSD and PSC; similarly, TCB relates to ( PSC / PSB ), and TBA to ( PSB / PSA ). 6T B C 7T C D

8 TDC

10 TBA

11 PSA Power supply enable output pins. These four pins control loads, such as DC/DC converter modules, load switches, ICs, etc. Confi gured with open drain output stages. On power-up, right after expiration of the PUD delay, the sequencer asserts PSA, and subsequently asserts PSB, PSC and PSD observing the delays, programmed by the (TAB, TBC, and TCD) pins. On power-down, the sequencer deasserts PSD, and subsequently deasserts PSC, PSB, and PSA observing the delays, programmed by the (TAB, TBC, and TCD) pins.

12 PSB

13 PSC

14 PSD

16 NC No connect

The fi gures of typical waveforms are organized in the following way: Figure Function Description 1, 2, 3, 4 PS (A, B, C, D) Power-up and power-down delays. Delay times around 5ms and 200ms. 5, 6 ON, PUD, PS (A, B, D) ON pin detail. Fig.6. shows a power-down / power-up sequence. 7, 8 PUD, PS (A, B) PUD pin detail; PSA is asserted when voltage at PUD pin about 1.2V. PUD pin resets when PSB is deasserted. 9 OV, PUD, PS (A, B) OV pin detail. Overvoltage returns to voltage window. 10 ON, PS (A, B, C) Partial power-up sequence. Power-down triggered by loss of valid ON. Fig.1 Fig.2 Fig.3 Fig.4

Fig.5 Fig.6 Fig.7 Fig.8 Fig.9 Fig.10

The PS12 provides power-up and power-down sequencing for devices such as power supply modules, load switches, ICs, etc. The four outputs PSA thru PSD are confi gured with open drain drivers, which are typically used to power supply modules. Some systems may require level-shifting or isolat- ing drivers. Upon application of power, the power-up delay timer is reset and the enable outputs PSA thru PSD are de-asserted. Window Comparator The state of the four PS outputs and the associated power- up and power-down sequencing is controlled by a window comparator formed by the ON and OV voltage compara- tors. These comparators defi ne a voltage window having thresh- olds programmed by an external resistive divider. The ON comparator defi nes the lower threshold of the window, while the OV comparator defi nes the upper threshold of the win- dow. Both comparator thresholds feature 200mV hyster- esis. Power-up and Power-down Sequence Power supply voltage moving into the window causes the start of a power-up sequence. The sequence consists of the power-up delay, programmed by C PUD, and the subsequent assertion of the PS outputs in the sequence ABCD using the enable to enable delays (T AB, TBC, TCD), as programmed by the resistors (RAB, RBC, RCD). Power supply voltage moving outside the window causes the start of a power-down sequence. The sequence consists of the de-assertion of the most recently asserted PS out- put, typically PSD, and subsequent de-assertion of other as- serted PS outputs in the sequence DCBA using the enable delays (T DC, TCB, TBA), as programmed by the resistors (RDC, RCB, RBA). The power-up sequence may be terminated prematurely by a power-down sequence. On the other hand, the pow- er-down sequence is latching in nature; once power-down is initiated, the sequence is brought to completion regard- less of changes in the state of the window comparator. After the power-down sequence is completed, a new power-up sequence may start, depending on the state of the window comparator at that time. Enable Outputs at Low VIN The internal circuits of the PS12 can be expected to provide well-defi ned outputs at a power supply voltage of about 3.3V and above. At lower power supply voltages, the existence of poorly defi ned output levels should typically not be an issue if the PS12 and the controlled loads share the same supply, since the loads may not be adequately biased as well. Some caution is warranted when the controlled loads are independently powered and the power supply voltage to the PS12 is inadequate or ill-defi ned. Delay Time Considerations The PS12 is characterized for enable to enable delay times between 5ms and 200ms, which should cover most applica- tions. Initial characterization of this device shows excellent linearity between delay time and programming resistance for a delay time in the range of 2.5ms to 5 seconds. Shorting of a programming pin is not advised, and may re- duce long term reliability, as internal circuits are not dimen- sioned for sourcing the resultant pin current. Power-up Delay (PUD) The power-up delay is set by the time required to charge the C PUD capacitor to 1.2V. The PUD pin sources a current of 12μA, resulting in a delay time of 100ms per µF. Charging continues past the power-up delay until a voltage of about 4V is reached. An internal voltage comparator at the PUD pin inhibits the power-up sequence, should the C PUD capacitor not be dis- charged before initiating the power-up delay. Discharge of the C PUD capacitor occurs during the power- down sequence. The discharge transistor is turned on at the end of the sequence when PSA is the last remaining as- serted output.

The ON and OV inputs draw negligible current, allowing the use of a high impedance divider. A divider current between 10µA and 100µA is more than adequate. V IN thresholds can be determined from the following: Start the design by programming the power-up voltage. The power-down voltage VINONPD is fi xed at 83.3% of the power- up voltage. Next, program the overvoltage power down volt- age V OVPD by selecting the multiplying factor R2 / R3, knowing VINONPU. A numerical example: VIN = 12V and [R1, R2, R3] = [107kΩ, 4.99kΩ, 9.09kΩ], results in the following: (1) RDIV = 121.1kΩ, (2) IDIV = 99.1µA, (3) [VINONPU, VINONPD, VINOVPD, VINOVPU] = Note the following: Programming the Power-up Delay The power-up delay (T PUD) is set by the time required to charge the CPUD capacitor to the threshold voltage VPUD: A numerical example: A 100nF capacitor results in a TPUD of 12ms. Programming the PS to PS Delay The PS to PS delays are set by the six timing resistors. De- lay time and resistance are related as follows: A numerical example: A resistance of 100kΩ results in a delay time of 10ms. OVPD 1.20V OVPU 1.10V OV ON ONPU 1.20V ONPD 1.10V R 2 R 3 R 1 VIN RDIV VINIDIV R3R2R1RDIV ++= ON Power-up: VONPU = 1.20V ON Power-down: VONPD = 1.00V OV Power-down: VOVPD = 1.20V OV Power-up: VOVPU = 1.00V R3R2 VONPU RDIV VINONPU R3R2 VONPD RDIV VINONPD VOVPD RDIV VINOVPD = R21R3 R3R2 20.1 20.1 R3R2 VONPU VOVPD VINONPU VINOVPD +=⎟⎟ ⎛ += IPUD CPUD • VPUDTPUD = VPUD = 1.20V IPUD = 12µA ns100KT RTKTTPSPS VOVPU RDIV VINOVPU =

(The package drawing(s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.#DSFP-PS12 NR042707 16-Lead SOIC (Narrow Body) Package Outline (NG) 9.90x3.90mm body, 1.75mm height (max), 1.27mm pitch Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1 Dimension (mm) 1.27 BSC 0.25 0.40 1.04 REF 0.25 BSC 0O 5O JEDEC Registration MS-012, Variation AC, Issue E, Sept. 2005. Drawings not to scale. D Seating Plane Gauge Plane L Top View Side View View A-A View B View B θ E1 E A A2 A A Seating Plane e b h h Note 1 Note 1 (Index Area D/2 x E1/2) Note 1: This chamfer feature is optional. If it is not present, then a Pin 1 identifi er must be located in the index area indicated.The Pin 1 identifi er may be either a mold, or an embedded metal or marked feature.