PS11

PS10 SUTEX | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 13

Technical content

Features

‰ Sequencing of Four or More* Supplies, ICs, or Sub- systems ‰ Independently Programmable Delays Between Open Drain PWRGD Flags (5ms to 200ms) ‰ ±10V to ±90V Operation ‰ Tracking in Combination with Schottky Diodes ‰ Input Supervisors Including: o UV/OV Lock Out/Enable o Power-On-Reset (POR) ‰ Low Power Consumption, 0.4mA Supply Current ‰ Small SO-14 Package *By Daisy-Chaining PS10/11’s

Applications

‰ Power Supply Sequencing ‰ -48V Telecom and Networking Distributed Systems ‰ -24V Cellular and Fixed Wireless Systems ‰ -24V PBX Systems ‰ +48V Storage Systems ‰ FPGA, Microprocessor Tracking ‰ Industrial/Embedded System Timing/Sequencing ‰ High Voltage MEMs Driver’s Supply Sequencing ‰ High Voltage Display Driver’s Supply Sequencing

Description

Many of today’s high performance FPGA’s, Microproces- sors, DSP and industrial/embedded subsystems require sequencing of the input power. Historically this has been accomplished: i) discretely using comparators, references & RC circuits; ii) using expensive programmable control- lers; or iii) with low voltage sequencers requiring resistor drop downs and several high voltage optocoupler or level shift components. The PS10/11 saves board space, improves accuracy, eliminates optocouplers or level shifts and reduces overall component count by combining four timers, programmable input UV/OV supervisors, a programmable POR and four 90V open drain outputs. A high reliability, high voltage, junction isolated process allows the PS10/11 to be con- nected directly across the high voltage input rails. The power-on-reset interval (POR) may be programmed by a capacitor on Cramp. To sequence additional sys- tems, PS10/11 may be daisy chained together. If at any time the input supply falls outside the UV/OV detector range the PWRGD outputs will immediately become IN- ACTIVE. Down sequencing may be accomplished with additional components (see page 11). The PS10/PS11 is available in a space saving SO-14 package. PS10 - Active High PS11 - Active Low A051204 Relative to Negative Rail Typical Application Circuit Waveform (49.9k pull-up on PS11 PWRGD pins) Initial Release RTB 9.76K 6.81K 487K RTD RTC /EN DC/DC CONVERTER DC/DC CONVERTER DC/DC CONVERTER /EN /EN DC/DC CONVERTER TB OV UV V /EN TC PWRGD-C / PWRGD-C PWRGD-D / PWRGD-D TD PWRGD-A / PWRGD-A PWRGD-B / PWRGD-B COM COM COM +2.5V +3.3V +5V +12V PS10/PS11 COM -48V or GND GND or +48V Notes: 1. Under Voltage Shutdown (UV) set to 37V. 2. Over Voltage Shutdown (OV) to 57.8V. 10nF Ramp V EE IN Supertex, Inc. • 1235 Bordeaux Drive, Sunnyvale, CA 94089 • Tel: (408) 222-8888 • FAX: (408) 222-4895 • www.supertex.com

2 A051204

*Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are refer- enced to device ground.

Ordering Information

14 Pin SOIC

Absolute Maximum Ratings* VEE referenced to VIN pin +0.3V to -100V VPWRGD referenced to VEE voltage -0.3V to +100V VUV and VOV referenced to VEE Voltage -0.3V to 12V Operating Ambient Temperature -40°C to +85°C Operating Junction Temperature -40°C to +125°C Storage Temperature Range -65° to +150°C Power Dissipation @ 25°C, 14-Pin SOIC 750mW Electrical Characteristics (-10V ≤ VIN ≤ -90V, TA = 25°C unless otherwise specified) Symbol Parameter Min Typ Max Units Conditions Supply (Referenced to VIN pin) VEE Supply Voltage -90 -10 V IEE Supply Current 400 450 µA VEE = -48V OV and UV Control (Referenced to VEE pin) VUVH UV High Threshold# 1.16 1.22 1.28 V Low to High Transition VUVL UV Low Threshold# 1.06 1.12 1.18 V High to Low Transition VUVHY UV Hysteresis# 100 mV IUV UV Input Current 1.0 nA VUV = VEE + 1.9V VOVH OV High Threshold# 1.16 1.22 1.28 V Low to High Transition VOVL OV Low Threshold# 1.06 1.12 1.18 V High to Low Transition VOVHY OV Hysteresis# 100 mV IOV OV Input Current 1.0 nA VUV = VEE + 1.9V #Specifications apply over 0°C ≤ TA ≤ 70°C Power Good Timing (Test Conditions: CRAMP = 10nF, VUV = VEE + 1.9V, VOV = VEE + 0.5V) IRAMP Ramp Pin Output Current µA tPWRGD-A Time from UV High to PWRGD-A 8.8 ms VEE = -48V, CRAMP = 10nF, see Typical Application Cir- cuit tPWRGD-B Maximum time from PWRGD-A to PWRGD-B 150 200* 250 ms RTB = 120kΩ tPWRGD-B Minimum time from PWRGD-A to PWRGD-B 3.0 5.0* 8.0 ms RTB = 3kΩ tPWRGD-C Maximum time from PWRGD-B to PWRGD-C 150 200* 250 ms RTC = 120kΩ tPWRGD-C Minimum time from PWRGD-B to PWRGD-C 3.0 5.0* 8.0 ms RTC = 3kΩ tPWRGD-D Maximum time from PWRGD-C to PWRGD-D 150 200* 250 ms RTD = 120kΩ tPWRGD-D Minimum time from PWRGD-C to PWRGD-D 3.0 5.0* 8.0 ms RTD = 3kΩ *Note: Variations will track. For example if tPWRGD-A is 250ms then so will be tPWRGD-B/C/D. Contact factory for tighter tolerance version. Power Good Outputs (Test Conditions: VUV = VEE + 1.9V, VOV = VEE + 0.5V) VPWRGD-x(hi) Power Good Pin Breakdown Voltage V PWRGD-x = HI Z VPWRGD-x(lo) Power Good Pin Output Low Voltage 0.4 0.5 V IPWRGD = 1mA, PWRGD-x = LOW IPWRGD-x(lk) Maximum Leakage Current <1.0 µA VPWRGD = 90V, PWRGD-x = HI Z

3 A051204

INACTIVE (not ready) VEE PS10 ACTIVE (Ready) HI Z INACTIVE (not ready) HI Z PS11 ACTIVE (Ready) VEE Pinout PWRGD-C (PS10) PWRGD-C (PS11) PWRGD-B (PS11) PWRGD-B (PS10) PWRGD-A (PS11) PWRGD-A (PS10) PWRGD-D (PS11) PWRGD-D (PS10) NC V UV OV V TD TC RAMP NC TB EE IN Top View Pin Description PWRGD-D – This open drain Power Good Output Pin is held inactive on initial power application and goes active a programmed time delay after PWRGD-C goes active. PWRGD-C – This open drain Power Good Output Pin is held inactive on initial power application and goes active a programmed time delay after PWRGD-B goes active. PWRGD-B – This open drain Power Good Output Pin is held inactive on initial power application and goes active a programmed time delay after PWRGD-A goes active. PWRGD-A – This open drain Power Good Output Pin is held inactive on initial power application and goes active one POR delay after the UV pin goes above its High threshold (provided VIN stays within the UV/OV window during this period). To function as an indicator a pullup resistor must be con- nected from this pin to a voltage rail no more than 90V from VEE. OV – This Over Voltage (OV) sense pin, when raised above its high threshold will immediately cause the Power Good Outputs to be pulled low. These outputs will remain low until the voltage on this pin falls below the low threshold limit, initiating a new start-up cycle. UV – This Under Voltage (UV) sense pin, when lowered below its low threshold will immediately cause the Power Good Outputs to be pulled low. These outputs will remain low until the voltage on this pin rises above the low thresh- old limit, initiating a new start-up cycle. VEE - This pin is the negative terminal of the power supply input to the circuit. VIN – This pin is the positive terminal of the power supply input to the circuit and can withstand 90V with respect to VEE. TD – The resistor connected from this pin to VEE pin sets the time delay from PWRGD-C going active to PWRGD-D going active. TC – The resistor connected from this pin to VEE pin sets the time delay from PWRGD-B going active to PWRGD-C going active. TB – The resistor connected from this pin to VEE pin sets the time delay from PWRGD-A going active to PWRGD-B going active. RAMP – This pin provides a current output so that a timing ramp is generated when a capacitor is connected. This tim- ing Ramp is used to program POR and the time from satis- faction of the UV/OV supervisors to PWRGD-A. NC– No Connect. This pin can be grounded or left floating.

4 A051204

& POR UVLO Vbg UV V V Band Gap Reference Programmable Timer TD PWRGD-B PWRGD-A PWRGD-C PWRGD-D TC TB Vint 10uA Vint RAMP OV Vint - 1.2V EE IN Functional Description The PS10/PS11 are designed to sequence up to 4 power supply modules, ICs or subsystems when the backplane voltage is within the programmed Under-voltage and Over- voltage limits. The power good open drain outputs are sequentially enabled starting from PWRGD-A to PWRGD- D. The time delay between power goods is programmable up to 200ms simply by changing the value(s) of RTB, RTC, and RTD. The initial time between satisfaction of the UV/OV supervisors & PWRGD-A can be programmed with Cramp. Description of Operation During the initial power application, the Power Good pins are held low (rising with VIN) for PS10 and high for the PS11. Once the internal under voltage lock out has been satisfied, the circuit checks the input supply under voltage (UV) and over voltage (OV) sense circuits to ensure that the input voltage is within programmed limits. These limits are determined by the selected values for R1, R2, and R3, which form a voltage divider. At the same time, a 10µA current source is enabled, charging the external capacitor connected to the ramp pin. The rise time of the ramp pin is determined by the value of the capacitor (10µA/Cramp). When the ramp voltage reaches 8.8V, the PWRGD-A pin will change into an active state. PWRGD-B will change into an active state after a programmed time delay from PWRGD-A inactive to active transition. PWRGD-C will change into an active state after a programmed time delay from PWRGD-B inactive to ac- tive transition. PWRGD-D will change into an active state after a programmed time delay from PWRGD-C inactive to active transition. The controller continuously monitors the UV and OV pins as long as the internal UVLO and POR circuits are satis- fied. At any time during the start up cycle or thereafter, crossing the UV low and OV high limits will cause an im- mediate discharge on Cramp and reset on the power good pins. When the input voltage returns to a value within the programmed UV and OV limits, a new start up sequence will initiate immediately. Programming the Under and Over Voltage Limits The UV and OV pins are connected to comparators with nominal 1.17V thresholds and 100mV of hysteresis (1.17V ± 50mV). They are used to detect under voltage and over voltage conditions at the input to the circuit. Whenever the OV pin rises above its high threshold (1.22V) or the UV pin falls below its low threshold (1.12V), the PWRGD outputs immediately deactivate. Calculations can be based on either the desired input volt- age operating limits or the input voltage shutdown limits. In the following equations the shutdown limits are assumed. The undervoltage and overvoltage shut down thresholds can be programmed by means of the three resistor divider formed by R1, R2 and R3. Since the input currents on the UV and OV pins are negligible the resistor values may be calculated as follows:

5 A051204

UVOFF = VUVL = 1.12 = (VEEUV(off)) x (R2+R3)/(R1+R2+R3) OVOFF = VOVL = 1.22 = (VEEOV(off)) x R3/(R1+R2+R3) Where (VEEUV(off)) and (VEEOV(off)) relative to VEE are Under and Over Voltage Shut Down Threshold points. If we select a divider current of 100 µA at a nominal oper- ating input voltage of 50 Volts, then R1+R2+R3 = 50V/100µA = 500kΩ From the second equation, for an OV shut down threshold of 65V, the value of R3 may be calculated. OVOFF = 1.22 = (65xR3)/500k R3 = (1.22x 500k)/65 = 9.38k The closest 1% value is 9.31kΩ. From the first equation, for a UV shut down threshold of 35V, the value of R2 can be calculated. UVOFF = 1.12 = 35 x (R2+R3)/ 500k 6.65kΩ is a standard 1% value Then R1 = 500k – R2 – R3 = 484.04kΩ. 487kΩ, is a standard 1% value. From the calculated resistor values the OV and UV start up threshold voltages can be calculated as follows: UVON = VUVH = 1.22 = (VEEUV(on)) x (R2+R3)/(R1+R2+R3) OVON = VOVL = 1.12 = (VEEOV(on)) x R3/(R1+R2+R3) Where (VEEUV(on)) and (VEEOV(on)) are Under and Over Volt- age Start Up Threshold points relative to VEE. Then (VEEUV(on)) = 1.22 x (R1+R2+R3)/(R2+R3) = 38.45V And (VEEOV(on)) = 1.12 x (R1+R2+R3)/R3 Therefore, the circuit will start when the input supply volt- age is in the range of 38.45V to 60.51V.

6 A051204

Undervoltage/Overvoltage Operation GND UVOFF UVON Vin OVON OVOFF PWRGD SET RESET Start-up Timing (PS11 PWRGD-A Active Low) tPWRGD-A is the time delay from VEEUV(on) to PWRGD-A going active. It can be approximated by tPWRGD-A = CRAMP x (VINT-1.17)/IRAMP where CRAMP = capacitor connected from RAMP pin to VEE pin VINT = internal regulated power supply voltage (10V typ) IRAMP = 10µA charge current PWRGD Flags Delay Programming When the ramp voltage hits Vint – 1.17V, PWRGD-A be- comes active indicating that the input supply voltage is within the programmed limits. PWRGD-B goes active after a programmed time delay after PWRGD-A went active. PWRGD-C goes active after a programmed time delay after PWRGD-B went active. PWRGD-D goes active after a programmed time delay after PWRGD-C went active. The resistors connected from TB, TC, and TD to VEE pin determines the delay times between the PWRGD flags. The value of the resistors determines the capacitor charg- ing and discharging current of a triangular wave oscillator. The oscillator output is fed into an 8-bit counter to gener- ate the desired time delay. The respective time delay is defined by the following equa- tion: tTX = (255 x 2 x COSC x VPP)/ICD and ICD = Vbg / (4 x RTX) Where tTX = Time delay between respective PWRGD flags COSC = 120pF (internal oscillator capacitor) VPP = 8.2V (peak-to-peak voltage swing of oscillator) ICD = Charge and discharge current of oscillator Vbg = 1.17V (internal band gap reference) RTX = Programming resistor at TB, TC, or TD Combining the two equations and solving for RTX yields: RTX = (Vbg x tTX) / (2040 x COSC x VPP) = 0.585 x 106 x tTX For a time delay of 200ms RTX = 0.585 x 106 x 0.2 = 117k For a time delay of 5ms RTX = 0.585 x 106 x 0.005 = 2.925k

7 A051204

The following waveforms demonstrate the sequencing of the PWRGD flags: PWRGD Timing (PS11) Test conditions: VIN = 48V, CRAMP = 10nF, RTB = 118k, RTC = 59k, and RTD = 46.4k. PWRGD Timing (Minimum Delays) Test conditions: VIN = 48V, CRAMP = 10nF, RTB = 3.24k, RTC = 3.24k, RTD = 3.24k, RPULL-UP = 47k. PWRGD Timing (Maximum Delays) Test conditions: VIN = 48V, CRAMP = 10nF, RTB = 118k, RTC = 118k, RTD = 118k, RPULL-UP = 47k. PS11 Power Down Sequence after UVOFF Test conditions: CRAMP = 10nF, RTB = 3.24k, RTC = 3.24k, RTD = 3.24k, RPULL-UP = 47k, CPWRGD_B = 0.47µF, CPWRGD_C = 0.94µF, CPWRGD_D = 1.41µF, VUVOFF = 33.4V, the as- sumed brick turn-off threshold is 2.7V min TTL logic high. See power down sequencing on Page 11. Relative to Negative Rail Relative to Negative Rail Relative to Negative Rail Relative to Negative Rail

8 A051204

PS11 Power Down Sequence after OVOFF Test conditions: CRAMP = 10nF, RTB = 3.24k, RTC = 3.24k, RTD = 3.24k, RPULL-UP= 47k, CPWRGD_B = 0.47µF, CPWRGD_C = 0.94µF, CPWRGD_D = 1.41µF, VOVOFF = 61.6V, the as- sumed brick turn-off threshold is 2.7V min TTL logic high. See power down sequencing on Page 11. PWRGD Output Configuration The PS10 and PS11 open drain power good outputs can be connected directly to the Enable pins of the DC/DC converter. The internal pull-up and clamp of the DC/DC converter sets the logic High Enable/Disable voltage. RTB 9.76K 6.81K 487K RTD RTC TB OV UV V TC PWRGD-C PWRGD-D TD PWRGD-A PWRGD-B PS10 -48V GND Notes: 1. Under Voltage Shutdown (UV) set to 37V. 2. Over Voltage Shutdown (OV) to 57.8V. 3. Other power good outputs will have the same configuration as PWGRGD-A for Active High Enabled Converters. 10nF Ramp COM +3.3V DC/DC Converter EN V IN EE Relative to Negative Rail

9 A051204

PWRGD Output Configuration, continued RTB 9.76K 6.81K 487K RTD RTC TB OV UV V TC PWRGD-C PWRGD-D TD PWRGD-A PWRGD-B PS11 -48V GND 10nF Ramp COM +3.3V DC/DC Converter /EN Notes: 1. Under Voltage Shutdown (UV) set to 37V. 2. Over Voltage Shutdown (OV) to 57.8V. 3. Other power good outputs will have the same configuration as PWGRGD-A for Active Low Enabled Converters. VEE IN Opto-isolated Enable Some applications require opto-isolator interface to the Enable pin of the DC/DC converter. Make sure that the current transfer ratio of the opto-coupler selected is at least 100% to ensure proper pull-down current on the Enable pin. RTB 9.76K 6.81K 487K RTD RTC 10nF Opto-coupler 49.9k PWRGD-A IN EN V GND TC EE TD OV DC/DC Converter COM PWRGD-B PWRGD-C UV Ramp -48V PS10 PWRGD-D V +3.3V TB Notes: 1. Under Voltage Shutdown (UV) set to 37V. 2. Over Voltage Shutdown (OV) to 57.8V. 3. Other power good outputs will have the same configuration as PWGRGD-A for Active High Enabled Converters.

10 A051204

Opto-isolated Enable, continued RTB 9.76K 6.81K 487K RTD RTC TB OV UV V TC PWRGD-C PWRGD-D TD PWRGD-A PWRGD-B PS11 -48V GND Notes: 1. Under Voltage Shutdown (UV) set to 37V. 2. Over Voltage Shutdown (OV) to 57.8V. 3. Other power good outputs will have the same configuration as PWGRGD-A for Active Low Enabled Converters. 10nF Ramp COM +3.3V DC/DC Converter /EN Opto-coupler 49.9k VEE IN Increasing the Under and Over Voltage Hysteresis If the internal UV hysteresis is insufficient for a particular system application, then it may be increased by using separate resis- tor dividers for UV and OV and providing a resistor feedback from UV pin to the PWRGD pin. RTB 16.5k 9.76k 487k RTD RTC TB OV UV V TC PWRGD-C PWRGD-D TD PWRGD-A PWRGD-B PS10 -48V GND Note: 1. Other power good outputs will have the same configuration as PWGRGD-A for Active High Enabled Converters. 2. Over voltage shut down set to 63.6V 10nF Ramp COM +3.3V DC/DC Converter EN Ruvhys 499k V IN EE Ruvhys can be calculated based on higher UV On voltage (say 42V): Ruvhys = (Vuvon - Vdiode - Vpwrgdlow)/((Vin-Vuvon)/487k - Vuvon/16.5k) = 17.35k

11 A051204

Increasing the Under and Over Voltage Hysteresis, continued RTB 16.5k 9.76k 487k RTD RTC TB OV UV V TC PWRGD-C PWRGD-D TD PWRGD-A PWRGD-B PS11 -48V GND Note: 1. Other power good outputs will have the same configuration as PWGRGD-A for Active Low Enabled Converters. 2. Over voltage shut down set to 63.6V 10nF Ramp COM +3.3V DC/DC Converter /EN Ruvhys 499k 10k V IN EE Ruvhys can be calculated based on higher UV On voltage (say 42V): Ruvhys = (Vuvon - Vdiode - Vce/((Vin-Vuvon)/487k - Vuvon/16.5k) = 47.97k Power Down Sequencing In some applications, a power down sequence may be required. To accomplish this, a capacitor is connected to the power good pins that need to be sequenced down. The power good turn off delays can be approximated by TPWRGD-B(off) = C1 x VENOFF / IPULLUP , TPWRGD-C(off) = C2 x VENOFF / IPULLUP , TPWRGD-D(off) = C3 x VENOFF / IPULLUP , where: TPWRGD-B(off) -Time delay from PWRGD-A going High to PWRGD-B going high. TPWRGD-c(off) -Time delay from PWRGD-A going High to PWRGD-C going high. TPWRGD-D(off) -Time delay from PWRGD-A going High to PWRGD-D going high. VENOFF - DC/DC minimum off voltage (2.7V typ) IPULLUP - DC/DC /EN pin pull-up current (1mA typ) Note: Adding C1, C2, C3 will have a negligible affect on the power good fall time. RTB 9.76K 6.81K 487K RTD RTC 10nF -48V GND PWRGD-C DC/DC Converter /EN PWRGD-B PS11 PWRGD-A Notes: 1. Under Voltage Shutdown (UV) set to 37V. 2. Over Voltage Shutdown (OV) to 57.8V. 3. Only PWRGD-A to DC/DC converter connection is shown for simplicity. PWRGD-D TD TC TB +3.3V COM Ramp /EN3 /EN2 OV UV /EN4 V EE IN V

12 A051204

If the active high enabled dc/dc converter used does not have an internal clamp, an external zener diode may be used to pro- tect the module. RTB 9.76K 6.81K 487K RTD RTC TB OV UV V TC PWRGD-C PWRGD-D TD PWRGD-A PWRGD-B PS10 -48V GND Notes: 1. Under Voltage Shutdown (UV) set to 37V. 2. Over Voltage Shutdown (OV) to 57.8V. 3. Other power good outputs will have the same configuration as PWGRGD-A for Active High Enabled Converters. 10nF Ramp COM +3.3V 49.9k DC/DC Converter EN VEE IN Typical Application Circuit for a 12V Non-Isolated System Most FPGAs, Processors, ASICs, and DSPs require sequencing and rail voltage limitation during start-up and power down sequence of its rails. A typical requirement is: VDD_CORE must not exceed VDD_IO more than 0.6V and VDD_IO must not ex- ceed VIN at any time. This can be accomplished by sequencing the dc/dc converters by the following manner: Turn On: VDD_CORE first, VDD_IO second, and VIN last. Tun-Off: VIN first, VDD_IO second, and VDD_CORE last. The Schottky diodes will limit the voltage between the rails to around 0.3V @ 3A during the power-up and power-down sequence. Assuming that the /EN pins of the dc/dc converters have no pull-up and have a 1.0V turn-off threshold, the power-down sequence time delays can be approximated by: TPWRGD-C to TPWRGD-B = 1µF x 1V / 1mA = 1ms TPWRGD-B to TPWRGD-A = (2µF-1µF) x 1V / 1mA = 1ms RTB RTD RTC Buck Converter Buck Converter /EN /EN Buck Converter TB OV UV V /EN TC PWRGD-C PWRGD-D TD PWRGD-A PWRGD-B +2.5V +5V PS11 GND +12V 10nF Ramp V EE IN +3.3V GND VDD_CORE LOAD VIN VDD_IO 30BQ015 30BQ015 12k 12k 1uF 2uF Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. 2004 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.

1235 Bordeaux Drive, Sunnyvale, CA 94089

TEL: (408) 222-8888 / FAX: (408) 222-4895 www.supertex.com A051204 Doc. #: DSFP-PS10PS11

1235 Bordeaux Drive, S unnyvale, CA 94089

TE L: (408) 222-8888 / F AX: (408) 222-4895 www.supertex.com A050604 ©2004 S upertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. TYP. 0° - 8 ° 45° 7° (4 PLCS ) 0.340 ± 0.005 (8.636 ± 0.127) D B 0.017 ± 0.003 (0.4318 ± 0.0762) 0.156 ± 0.002 (3.9624 ± 0.0508) E 0.500 (12.700) TYP. 0.350 (8.890) 0.2335 ± 0.0105 (5.9309 ± 0.2667) H 0.063 ± 0.005 (1.600 ± 0.127) A TYP. 0.050 (1.270) e 0.006 ± 0.002 (0.1524 ± 0.0508) 0.193 ± 0.012 (4.9022 ± 0.3048) 0.020 ± 0.009 (0.508 ± 0.2286) h C 0.006 ± 0.004 (0.1524 ± 0.1016) 0.035 ± 0.015 (0.889 ± 0.381) L 0.0275 ± 0.0025 (0.6985 ± 0.0635) Note: Circle (e.g. B ) indicates JE DE C R eference. Dimensions in Inches (Dimensions in Millimeters) Measurement Legend = 14-LEAD SO PACKAGE (NG) (NARROW BODY) Doc. #: DSPD14SONG