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Technical content
µTrenchMOS™ ultra low level FET 1. Product profile
1.1 Description
N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS™ technology. Product availability: PMV30UN in SOT23.
1.2 Features
1.3 Applications
1.4 Quick reference data
- Pinning information ■ Surface mount package ■ Fast switching. ■ Battery management ■ High-speed switches. ■ V DS ≤ 20 V ■ I D ≤ 5.7 A ■ P tot ≤ 1.9 W ■ R DSon ≤ 36 mΩ Table 1: Pinning - SOT23 simplified outline and symbol Pin
Description
Simplified outline Symbol 1 gate (g) SOT23 2 source (s) 3 drain (d) MSB003 Top view s d g MBB076 1 of 3sales@zpsemi.com www.zpsemi.com
- Limiting values Table 2: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit V DS drain-source voltage (DC) 25 °C ≤ T j ≤ 150 °C - 20 V V DGR drain-gate voltage (DC) 25 °C ≤ T j ≤ 150 °C; R GS =2 0kΩ -2 0 V V GS gate-source voltage (DC) - ±8V I D drain current (DC) T sp =2 5°C; V GS = 4.5 V;Figure 2and 3 - 5.7 A T sp = 100°C; V GS = 4.5 V;Figure 2 - 3.65 A I DM peak drain current T sp =2 5°C; pulsed; t p ≤ 10 µs;Figure 3 - 23.1 A P tot total power dissipation T sp =2 5°C; Figure 1 - 1.9 W T stg storage temperature −55 +150 °C T j junction temperature −55 +150 °C Source-drain diode I S source (diode forward) current (DC) T sp =2 5°C - 1.6 A I SM peak source (diode forward) current T sp =2 5°C; pulsed; t p ≤ 10 µs - 6.4 A PMV30UN µTrenchMOS™ ultra low level FET 2 of 3sales@zpsemi.com www.zpsemi.com
- Characteristics Table 3: Characteristics T j =2 5 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Static characteristics V (BR)DSS drain-source breakdown voltage I D = 250µA; V GS =0V T j =2 5°C 2 0 --V T j = −55 °C 1 8 --V V GS(th) gate-source threshold voltage I D = 1 mA; V DS GS ;Figure 9 T j T j = 150°C 0.25 0.4 - V I DSS drain-source leakage current V DS =2 0V ; V GS =0V T j =2 5°C --1 µA T j = 150°C - - 100 µA I GSS gate-source leakage current V GS = ±8 V; V DS = 0 V - 10 100 nA R DSon drain-source on-state resistance V GS = 4.5 V; I D =2A ;Figure 7and 8 T j =2 5°C - 30 36 m Ω T j = 150°C - 48 57.6 m Ω V GS = 2.5 V; I D = 1.5 A;Figure 7and 8 - 3 64 3m Ω V GS = 1.8 V; I D =1A ;Figure 7and 8 - 4 46 3m Ω Dynamic characteristics Q g(tot) total gate charge I D = 5 A; V DD =1 0V ; V GS = 4.5 V;Figure 13 - 7.4 - nC Q gs gate-source charge - 1.2 - nC Q gd gate-drain (Miller) charge - 1.8 - nC C iss input capacitance V GS =0V ; V DS = 20 V; f = 1 MHz;Figure 11 - 460 - pF C oss output capacitance - 100 - pF C rss reverse transfer capacitance - 70 - pF t d(on) turn-on delay time V DD =1 0V ; R L =1 0Ω ; V GS = 4.5 V; R G =6 Ω -7 -n s t r rise time -1 3 -n s t d(off) turn-off delay time - 53 - ns t f fall time -1 3 -n s Source-drain diode V SD source-drain (diode forward) voltage I S = 1.7 A; V GS =0V ;Figure 12 - 0.81 1.2 V PMV30UN µTrenchMOS™ ultra low level FET 3 of 3sales@zpsemi.com www.zpsemi.com