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Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
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Technical content

  1. Product profile

1.1 General description

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS™ technology.

1.2 Features

1.3 Applications

1.4 Quick reference data

  1. Pinning information PMV117EN µTrenchMOS™ enhanced logic level FET ■ Logic level threshold ■ Very fast switching ■ Subminiature surface-mounted package ■ Battery management ■ Low power DC-to-DC converter ■ High-speed switch ■ V DS ≤ 30 V ■ I D ≤ 2.5 A ■ R DSon ≤ 117 mΩ (V GS =1 0V ) ■ P tot ≤ 0.83 W Table 1: Pinning Pin

Description

Simplified outline Symbol 1 gate (G) SOT23 2 source (S) 3 drain (D) S D G mbb076 1 of 3sales@zpsemi.com www.zpsemi.com

  1. Ordering information 4. Limiting values Table 2: Ordering information Type number Package Name

PMV117EN TO-236AB plastic surface mounted package; 3 leads SOT23 Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit V DS drain-source voltage (DC) 25 °C ≤ T j ≤ 150 °C - 30 V V DGR drain-gate voltage (DC) 25 °C ≤ T j ≤ 150 °C; R GS =2 0kΩ -3 0 V V GS gate-source voltage (DC) - ±20 V I D drain current (DC) T sp =2 5°C; V GS =1 0V ; Figure 2 and 3 - 2.5 A T sp = 100°C; V GS =1 0V ; Figure 2 - 1.6 A I DM peak drain current T sp =2 5°C; pulsed; t p ≤ 10 µs; Figure 3 -1 0 A P tot total power dissipation T sp =2 5°C; Figure 1 - 0.83 W T stg storage temperature −65 +150 °C T j junction temperature −65 +150 °C Source-drain diode I S source (diode forward) current (DC) T sp =2 5°C - 0.8 A I SM peak source (diode forward) current T sp =2 5°C; pulsed; t p ≤ 10 µs - 3.3 A PMV117EN µTrenchMOS™ enhanced logic level FET 2 of 3sales@zpsemi.com www.zpsemi.com

  1. Characteristics Table 4: Characteristics T j =2 5 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Static characteristics V (BR)DSS drain-source breakdown voltage I D =1 0µA; V GS =0V T j =2 5°C 3 03 7- V T j = −55 °C2 7 - - V V GS(th) gate-source threshold voltage I D = 1 mA; V DS GS Figure 9 and T j =2 5°C 1.5 2 - V T j = 150°C 1.1 - - V T j = −55 °C - - 2.7 V I DSS drain-source leakage current V DS =2 4V ; V GS =0V T j =2 5°C - 0.01 0.5 µA T j = 150°C --1 0 µA I GSS gate-source leakage current V GS = ±20 V; V DS = 0 V - 10 100 nA R DSon drain-source on-state resistance V GS =1 0V ; I D = 500 mA; Figure 6 and T j =2 5°C - 74 117 m Ω V GS = 4.5 V; I D = 500 mA; Figure 6 and 8 - T j =2 5°C - 117 190 m Ω T j = 150°C 188 300 m Ω Dynamic characteristics Q g(tot) total gate charge I D = 0.5 A; V DD =1 5V ; V GS =1 0V ; Figure - 4.6 - nC Q gs gate-source charge - 0.6 - nC Q gd gate-drain (Miller) charge - 1.35 - nC C iss input capacitance V GS =0V ; V DS = 10 V; f = 1 MHz; Figure - 147 - pF C oss output capacitance - 65 - pF C rss reverse transfer capacitance - 41 - pF t d(on) turn-on delay time V DD =1 5V ; R L =1 5Ω ; V GS =1 0V - 4 - n s t r rise time - 7.5 - ns t d(off) turn-off delay time - 18 - ns t f fall time -1 3 -n s Source-drain diode V SD source-drain (diode forward) voltage I S = 0.83 A; V GS =0V ; Figure 12 - 0.7 1.2 V t rr reverse recovery time I S = 1 A; dI S /dt =−100 A/µs; V GS =0V ; V DS =2 5V -6 9 -n s PMV117EN µTrenchMOS™ enhanced logic level FET 3 of 3sales@zpsemi.com www.zpsemi.com