PE5A1BA UNIKC | Alldatasheet

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P-Channel Logic Level Enhancement Mode MOSFET PRODUCT SUMMARY V(BR)DSS PDFN 3x3P ABSOLUTE MAXIMUM RATINGS (TA = 25 ° C Unless Otherwise Noted) TJ, TSTG TC = 25 ° C TC = 100 ° C EASAvalanche Energy L = 0.1mH RDS(ON) TC = 100 ° C PARAMETERS/TEST CONDITIONS Drain-Source Voltage Gate-Source Voltage 6.5mΩ @VGS = -4.5V -43A ID -20V SYMBOL VDS Pulsed Drain Current1 ID TC = 25 ° C IDM Avalanche Current IAS Junction & Storage Temperature Range -18 -43 -39 -14 3.5 2.2 -20 VGS LIMITS °C-55 to 150 mJ UNITS -50 V A W Continuous Drain Current4 Power Dissipation3 TA = 25 ° C TA = 70 ° C TA = 25 ° C TA = 70 ° C -27 PD REV1.1 1 2015/10/14

P-Channel Logic Level Enhancement Mode MOSFET THERMAL RESISTANCE RATINGS UNITS 1Pulse width limited by maximum junction temperature. 2The value of RqJA is measured with the device mounted on 1 in2 FR-4 board with 2oz. Copper, in a still air environment with TA = 25° C. 3The Power dissipation is based on RqJA t ≦10s value. 4Package limitation current is 36A. ELECTRICAL CHARACTERISTICS (TJ = 25 ° C, Unless Otherwise Noted) MIN TYP MAX -20 -0.45 -0.6 -0.9 ± 100 nA -10 4.9 6.5 6 8 7.6 11 47 S 5926 551 424 4 Ω 6.7 12.7 190 109 TEST CONDITIONS Drain-Source On-State Resistance1 RDS(ON) Gate Threshold Voltage IDSS VGS = 0V, ID = -250mAV(BR)DSS nSVDD = -10V, ID @ -3.5A, VGS = -4.5V, RGEN = 6Ω Rise Time2 Turn-Off Delay Time2 td(on) tr td(off) tfFall Time2 Turn-On Delay Time2 THERMAL RESISTANCE SYMBOL TYPICAL mA mΩ DYNAMIC VDS = -16V, VGS = 0V LIMITS nC VGS = 0V, VDS = -10V, f = 1MHz pF Ciss Coss VGS = -2.5V, ID = -3.5A VGS = -1.8V, ID = -2A Input Capacitance Output Capacitance Forward Transconductance1 Reverse Transfer Capacitance Crss VDS = -10V, VGS = 0V , TJ = 55 ° C VGS = -4.5V, ID = -3.5A VDS = -10V, ID = -3.5A Zero Gate Voltage Drain Current gfs UNITSPARAMETER V IGSS Drain-Source Breakdown Voltage VGS(th) Gate-Body Leakage VDS = VGS, ID = -250mA VDS = 0V, VGS = ± 8V SYMBOL MAXIMUM 60Steady-State RqJA Junction-to-Ambient2 Junction-to-Ambient2 t ≦10s 35 RqJA Qg(VGS=-4.5V) VDS = -10V, ID = -3.5A STATIC Total Gate Charge2 Qg(VGS=-2.5V) Gate-Drain Charge2 Gate-Source Charge2 Qgd Qgs Gate Resistance Rg VGS = 0V, VDS = 0V, f = 1MHz Junction-to-Case Steady-State RqJC 6 ° C / W REV1.1 2 2015/10/14

P-Channel Logic Level Enhancement Mode MOSFET -15 A -1.3 V 37 nS 26 nC 1Pulse test : Pulse Width  300 msec, Duty Cycle  2％. 2Independent of operating temperature. IF = -3.5A, dl/dt = 100A / mS Reverse Recovery Charge trr Continuous Current IS Qrr Forward Voltage1 VSD IF = -3.5A, VGS = 0V SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TJ = 25 ° C) Reverse Recovery Time REV1.1 3 2015/10/14

P-Channel Logic Level Enhancement Mode MOSFET REV1.1 4 2015/10/14

P-Channel Logic Level Enhancement Mode MOSFET REV1.1 5 2015/10/14

P-Channel Logic Level Enhancement Mode MOSFET REV1.1 6 2015/10/14

P-Channel Logic Level Enhancement Mode MOSFET A. Marking Information(此产品代码为：L7） B. Tape&Reel Information:5000pcs/Reel REV1.1 7 2015/10/14

P-Channel Logic Level Enhancement Mode MOSFET REV1.1 8 2015/10/14

P-Channel Logic Level Enhancement Mode MOSFET D.Label rule 标签内容(Label content) REV1.1 9 2015/10/14