PE597BA UNIKC | Alldatasheet

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P-Channel Logic Level Enhancement Mode MOSFET PRODUCT SUMMARY V(BR)DSS PDFN 3x3P ABSOLUTE MAXIMUM RATINGS (TA = 25 ° C Unless Otherwise Noted) TC = 25 ° C TC = 100 ° C EASAvalanche Energy L = 0.1mH RDS(ON) TC = 100 ° C PARAMETERS/TEST CONDITIONS Drain-Source Voltage Gate-Source Voltage 35mΩ @VGS = -4.5V -17A ID -20V VDS Pulsed Drain Current1 ± 12 ID TC = 25 ° C TJ, TSTG IDM Avalanche Current IAS Junction & Storage Temperature Range °C-55 to 150 mJ UNITS -28 V A-7 -17 -14 -11 PD -20 VGS LIMITS SYMBOL W Continuous Drain Current4 Power Dissipation3 TA = 25 ° C TA = 70 ° C TA = 25 ° C TA = 70 ° C REV1.0 1 2016/12/8

P-Channel Logic Level Enhancement Mode MOSFET THERMAL RESISTANCE RATINGS UNITS 1Pulse width limited by maximum junction temperature. 2The value of RqJA is measured with the device mounted on 1 in2 FR-4 board with 2oz. Copper, in a still air environment with TA = 25° C. 3The Power dissipation is based on RqJA t ≦10s value. 4Package limitation current is 36A. ELECTRICAL CHARACTERISTICS (TJ = 25 ° C, Unless Otherwise Noted) MIN TYP MAX -20 -0.7 -0.8 -1.3 ± 100 nA -10 32 55 22 35 16 S 767 117 13 Ω 5.5 8.8 2.6 Junction-to-Ambient2 Steady-State RqJA 75 td(off) tfFall Time2 Turn-On Delay Time2 TEST CONDITIONS Drain-Source On-State Resistance1 RDS(ON) Gate Threshold Voltage IDSS VGS = 0V, ID = -250mA nSVDD = -10V, ID @ -3.5A, VGS = -4.5V, RGEN = 6Ω Rise Time2 Turn-Off Delay Time2 td(on) THERMAL RESISTANCE SYMBOL TYPICAL mA mΩ DYNAMIC VDS = -16V, VGS = 0V LIMITS nC VGS = 0V, VDS = -10V, f = 1MHz pF Ciss Coss VGS = -4.5V, ID = -3.5A Input Capacitance Output Capacitance Forward Transconductance1 Reverse Transfer Capacitance Crss VDS = -10V, VGS = 0V , TJ = 55 ° C VGS = -2.5V, ID = -3.5A VDS = -5V, ID = -3.5A Zero Gate Voltage Drain Current gfs Drain-Source Breakdown Voltage VGS(th) Gate-Body Leakage VDS = VGS, ID = -250mA VDS = 0V, VGS = ± 12V SYMBOL V(BR)DSS MAXIMUM RqJA 40 Qg(VGS=-2.5V) VDS = -10V, ID = -3.5A STATIC UNITSPARAMETER V IGSS Total Gate Charge2 Qg(VGS=-4.5V) Gate-Drain Charge2 Gate-Source Charge2 Qgd Qgs tr Gate Resistance Rg VGS = 0V, VDS = 0V, f = 1MHz RqJC 8 ° C / W t ≦10sJunction-to-Ambient2 Steady-StateJunction-to-Case REV1.0 2 2016/12/8

P-Channel Logic Level Enhancement Mode MOSFET -1 A -1.3 V 9.5 nS 3 nC 1Pulse test : Pulse Width  300 msec, Duty Cycle  2％. 2Independent of operating temperature. IF = -3.5A, dl/dt = 100A / mS Reverse Recovery Charge trr Continuous Current IS Qrr Forward Voltage1 VSD IF = -3.5A, VGS = 0V SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TJ = 25 ° C) Reverse Recovery Time REV1.0 3 2016/12/8

P-Channel Logic Level Enhancement Mode MOSFET REV1.0 4 2016/12/8

P-Channel Logic Level Enhancement Mode MOSFET REV1.0 5 2016/12/8

P-Channel Logic Level Enhancement Mode MOSFET REV1.0 6 2016/12/8

P-Channel Logic Level Enhancement Mode MOSFET A. Marking Information(此产品代码为：M3） B. Tape&Reel Information:5000pcs/Reel REV1.0 7 2016/12/8

P-Channel Logic Level Enhancement Mode MOSFET REV1.0 8 2016/12/8

P-Channel Logic Level Enhancement Mode MOSFET D.Label rule 标签内容(Label content) REV1.0 9 2016/12/8