PE537BA UNIKC | Alldatasheet
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P-Channel Logic Level Enhancement Mode MOSFET PRODUCT SUMMARY V(BR)DSS PDFN 3X3P ABSOLUTE MAXIMUM RATINGS (TA = 25 ° C Unless Otherwise Noted) THERMAL RESISTANCE RATINGS UNITS 1Pulse width limited by maximum junction temperature. 2The value of RqJA is measured with the device mounted on 1in2 FR-4 board with 2oz. Copper, in a still air environment with TA =25° C. 3Package limitation current is 22A. A TA = 25 ° C ID Pulsed Drain Current1 V 7.5 ° C / W 16.7 -33 -100 mJ -12 W 57.8 °C-55 to 150 SYMBOL IDM VGS Junction & Storage Temperature Range SYMBOL Avalanche Current IAS -34 UNITS -22 TYPICAL VDS -30 V LIMITS TC = 25 ° C EAS MAXIMUM Junction-to-Ambient2 THERMAL RESISTANCE Avalanche Energy L =0.1mH -30V TC = 100 ° C PARAMETERS/TEST CONDITIONS RDS(ON) Drain-Source Voltage 8.5mΩ @VGS = -10V -33A Gate-Source Voltage TA= 70 ° C -9.6 TA = 25 ° C 2 ID TC = 25 ° C Junction-to-Case ± 20 6.7 TA = 70 ° C 1.3 RqJC RqJA Continuous Drain Current3 Power Dissipation PD TC = 100 ° C TJ, Tstg REV 1.0 1 2015/1/7
P-Channel Logic Level Enhancement Mode MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25 ° C, Unless Otherwise Noted) MIN TYP MAX -30 -1 -1.6 -3 ± 100 nA -10 9.9 14 6.9 8.5 35 S 2803 371 286 4 Ω 100 -12.8 A -1.3 V 26 nS 14 nC 1Pulse test : Pulse Width 300 msec, Duty Cycle 2％. 2Independent of operating temperature. VDS = VGS, ID = -250mA VGS = 0V, ID = -250mA Gate-Body Leakage VGS(th) UNITS Coss Drain-Source Breakdown Voltage V Zero Gate Voltage Drain Current IGSS IF = -12A, dl/dt = 100A / mS VGS = -4.5V, ID =-12A Forward Transconductance1 STATIC V(BR)DSS TEST CONDITIONS nC VGS = 0V, VDS = 0V, f = 1MHz Qgs mA DYNAMIC mΩ VDS = -24V, VGS = 0V Qgd pF IDSS QrrReverse Recovery Charge Continuous Current Forward Voltage1 Reverse Recovery Time IS VSD trr IF = -12A, VGS = 0V nSVDD= -10V, ID @ -12A, VGS = -10V, RGEN= 6Ω SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TJ = 25 ° C) td(on) tr td(off) tf Turn-On Delay Time2 Rise Time2 Turn-Off Delay Time2 Fall Time2 Gate Threshold Voltage Drain-Source On-State Resistance1 Rg VDS = -15V ,ID = -12A VDS = -10V, ID = -12A VDS = 0V, VGS = ± 20V Crss LIMITS Ciss gfs RDS(ON) Output Capacitance VGS = -10V , ID = -12A VDS = -20V, VGS = 0V, TJ = 55 ° C SYMBOL Gate-Drain Charge2 Gate-Source Charge2 Reverse Transfer Capacitance Gate Resistance Qg(VGS= -10V) Total Gate Charge2 Qg(VGS= -4.5V) Input Capacitance VGS = 0V, VDS = -15V, f = 1MHz PARAMETER REV 1.0 2 2015/1/7
P-Channel Logic Level Enhancement Mode MOSFET REV 1.0 3 2015/1/7
P-Channel Logic Level Enhancement Mode MOSFET REV 1.0 4 2015/1/7
P-Channel Logic Level Enhancement Mode MOSFET REV 1.0 5 2015/1/7