PD563BA UNIKC | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 8

Technical content

P-Channel Enhancement Mode MOSFET PRODUCT SUMMARY V(BR)DSS TO-252 ABSOLUTE MAXIMUM RATINGS (TA = 25 ° C Unless Otherwise Noted) THERMAL RESISTANCE RATINGS UNITS 1Pulse width limited by maximum junction temperature. 2Package limitation current is -39A. 2Junction-to-Case RqJC L = 0.1mH EAS 57.8 mJ 62.5 ° C / W SYMBOL W Avalanche Current IAS -34 TC= 100° C Junction & Storage Temperature Range Power Dissipation Tj, Tstg -55 to 150 PD Avalanche Energy MAXIMUMTHERMAL RESISTANCE Continuous Drain Current3 TC= 100 ° C PARAMETERS/TEST CONDITIONS 15mΩ @VGS = -10V -46A Drain-Source Voltage Pulsed Drain Current1 Gate-Source Voltage -40V RDS(ON) Junction-to-Ambient TYPICA L ID TC= 25 ° C TC= 25 ° C RqJA ID V UNITS -130 -29 -40 ± 25 VDS AIDM 62.5 SYMBOL -46 LIMITS VVGS REV 1.0 1 2017/1/13

P-Channel Enhancement Mode MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25 ° C, Unless Otherwise Noted) MIN TYP MAX -40 -1 -1.5 -3 ± 100 nA -10 12.5 15 16.3 29 42 S 1881 256 207 4 Ω 3.7 -46 A -1.3 V 16 nS 6 nC 1Pulse test : Pulse Width  300 msec, Duty Cycle  2%. 2Independent of operating temperature. 3Package limitation current is -39A. VDS = -5V, ID = -20A TEST CONDITIONS Forward Transconductance1 VDS =-30V, VGS = 0V, TJ = 55° C VGS = -10V, ID = -20A IGSS VGS(th) PARAMETER Zero Gate Voltage Drain Current gfs LIMITS Gate-Body Leakage Drain-Source Breakdown Voltage VGS = 0V, VDS = -20V, f = 1MHz SYMBOL Output Capacitance DYNAMIC VGS = -4.5V, ID = -15A VDS =-32V, VGS = 0V mA Gate-Source Charge2 Reverse Transfer Capacitance Qg(VGS=-10V) Input Capacitance Total Gate Charge2 VDS =-20V,ID = -20A Gate Resistance SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TJ = 25 ° C) Rise Time2 VGS =0V, VDS = 0V, f = 1MHz QrrReverse Recovery Charge Continuous Current3 Forward Voltage1 Reverse Recovery Time Fall Time2 tf VSD tr pF Turn-On Delay Time2 Drain-Source On-State Resistance1 RDS(ON) VGS = 0V, ID = -250mA nC Qg(VGS=-4.5V) Ciss V Qgd Qgs Turn-Off Delay Time2 Gate-Drain Charge2 VDS =-20V ,ID @ -20A, VGS=-10V,RGEN=6Ω td(on) V(BR)DSS Gate Threshold Voltage STATIC nS trr Rg mΩ IF = -20A, VGS = 0V UNITS IF = -20A, dlF/dt = 100A /mS VDS = 0V, VGS = ± 25V IDSS Coss Crss td(off) IS VDS = VGS, ID = -250mA REV 1.0 2 2017/1/13

P-Channel Enhancement Mode MOSFET REV 1.0 3 2017/1/13

P-Channel Enhancement Mode MOSFET REV 1.0 4 2017/1/13

P-Channel Enhancement Mode MOSFET *因为各家封装模具不同而外观略有所差异,不影响电性及Layout。 REV 1.0 5 2017/1/13

P-Channel Enhancement Mode MOSFET A. Marking Information B. Tape&Reel Information:2500pcs/Reel REV 1.0 6 2017/1/13

P-Channel Enhancement Mode MOSFET REV 1.0 7 2017/1/13

P-Channel Enhancement Mode MOSFET D.Label rule 标签内容(Label content) REV 1.0 8 2017/1/13