PBM3960

PBM3960-1 ERICSSON | Alldatasheet

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Technical content

Description

PBM 3960/1 is a dual 7-bit+sign, Digital-to-Analog Converter (DAC) especially developed to be used together with the PBL 3771/1, Precision Stepper Motor driver in micro-stepping applications. The circuit has a set of input registers connected to an 8-bit data port for easy interfacing directly to a microprocessor. Two registers are used to store the data for each seven-bit DAC, the eighth bit being a sign bit (sign/ magnitude coding). A second set of registers are used for automatic fast/slow current decay control in conjunction with the PBL 3771/1, a feature that greatly improves high-speed micro-stepping performance. The PBM 3960/1 is fabricated in a high- speed CMOS process. Key Features

• Analog control voltages from 3 V down to 0.0 V.
• High-speed microprocessor interface.
• Automatic fast/slow current decay control.
• Full-scale error ±1 LSB.
• Interfaces directly with TTL levels and CMOS devices.
• Fast conversion speed, 3 µs.
• Matches PBL 3771. PBM 3960/1 Microstepping Controller/ Dual Digital-to-Analog Converter February 1999

Figure 1. Block Diagram.

Electrical Characteristics

Electrical characteristics over recommended operating conditions. Ref. Parameter Symbol fig Conditions Min Typ Max Unit Logic Inputs Reset logic HIGH input voltage VIHR 3.5 V Reset logic LOW input voltage VILR 0.1 V Logic HIGH input voltage V IH 2.0 V Logic LOW input voltage V IL 0.8 V Reset input current I IR VSS < VIR < VDD -0.01 1 mA Input current, other inputs II VSS < VI < VDD -1 1 µA Input capacitance 3p F Internal Timing Characteristics Address setup time t as 2 Valid for A0, A1 60 ns Data setup time t ds 2 Valid for D0 - D7 60 ns Chip select setup time t cs 27 0 n s Address hold time t ah 20 n s Data hold time t dh 20 n s Chip select hold time t ch 20 n s Write cycle length t WR 25 0 n s Reset cycle lenght t R 38 0 n s Reference Input Input resistance R Ref 69 k Ω Logic Outputs Logic HIGH output current IOH VO = 2.4 V -13 -5 mA Logic LOW output current I OL VO = 0.4 V 1.7 5 mA Write propagation delay t pWR 2 From positive edge of WR. 30 100 ns outputs valid, Cload = 120 pF Reset propagation delay t pR 3 From positive edge of Reset to 60 150 ns outputs valid, Cload = 120 pF DAC Outputs Reset open, VRef = 2.5 V Nominal output voltage V DA 0V Ref- 1LSB V Resolution 7 Bits Offset error 7 0.2 0.5 LSB Gain error 7 0.1 0.5 LSB Endpoint nonlinearity 7 0.2 0.5 LSB Differential nonlinearity 5, 6 0.2 0.5 LSB Load error (V DA , unloaded - VDA , loaded) 0.1 0.5 LSB R load = 2.5 kΩ , Code 127 to DAC Power supply sensitivity Code 127 to DAC 0.1 0.3 LSB 4.75 V < VDD < 5.25 V Conversion speed t DAC 2 For a full-scale transition to ±0.5 LSB 3 8 µs of final value, Rload = 2.5 kohm, Cload = 50 pF.

Figure 4. Pin configuration. 21 0 D A 1 Digital-to-Analog 1, voltage output. Output between 0.0 V and VR - 1 LSB. 3 12 Sign 1 Sign 1, TTL/CMOS level. To be connected directly to PBL 3771 Phase input. Databit D7 is transfered non inverted from PBM 3960/1/1 data input. decay level is programmed. LOW level = fast current decay. DD Voltage Drain-Drain, logic supply voltage. Normally +5 V. 6 15 WR Write, TTL/CMOS level, input for writing to internal registers. Data is clocked into flip flops on positive edge. 7 16 D7 Data 7, TTL/CMOS level, input to set data bit 7 in data word. 8 17 D6 Data 6, TTL/CMOS level, input to set data bit 6 in data word. 9 19 D5 Data 5, TTL/CMOS level, input to set data bit 5 in data word. 10 20 D4 Data 4, TTL/CMOS level, input to set data bit 4 in data word. 11 21 D3 Data 3, TTL/CMOS level, input to set data bit 3 in data word. 12 23 D2 Data 2, TTL/CMOS level, input to set data bit 2 in data word. 13 24 D1 Data 1, TTL/CMOS level, input to set data bit 1 in data word. 14 25 D0 Data 0, TTL/CMOS level, input to set data bit 0 in data word. A0 selects between cannel 1 (A0 = LOW) and channel 2 (A0 = HIGH). D/A register programming (A1 = LOW) and decay level register programming (A1 = HIGH). from data inputs. LOW level = chip is selected. measurements unless otherwise noted. when decay level is programmed. LOW level = fast current decay . 2 Sign 2. TTL/CMOS level. To be connected directly to PBL 3771 sign input. Data bit D7 is transfered non-inverted from PBM 3960/1 data input. 2 Digital-to-Analog 2, voltage output. Output between 0.0 V and Vref - 1 LSB. 22 7 Reset Reset, digital input resetting internal registers. HIGH level = Reset, VRes ≥ 3.5 V = HIGH level. Pulled low internally.

5 Not Connected

8 Not Connected

11 Not Connected

18 Not Connected

22 Not Connected

26 Not Connected

grammed in channel 2’s level register. Data value, sign bit excluded. outputs and all digital outputs. Figure 10. Table showing how data is transfered inside PBM 3960/1. Figure 9. Motor current dragging at high step rates and current decay influence. curve. Output shown without sign shift. available from each driver stage. tailored for specific damping needs etc.

1 X X No Transfer

proportional to the current in resp. winding it is possible to draw figure 8b.

increase on the positive edge of the sine- cosine curves. Fast current decay is used at higher speeds to avoid current dragging with lost positions and incorrect step angles as a result. Ramping Every drive system has inertia which must be considered in the drive system. The rotor and load inertia play a big role at higher speeds. Unlike the DC motor, the stepper motor is a synchronous motor and does not change its speed due to load variations. Examining a typical stepper motor’s torque-versus- speed curve indicates a sharp torque drop-off for the “start-stop without error” curve. The reason for this is that the torque requirements increase by the cube of the speed change. For good motor performance, controlled accelera- tion and deceleration should be conside- red even though microstepping will improve overall performance. Programming PBM 3960/1 There are basically two different ways of programming the PBM 3960/1. They are called “single-pulse programming” and “double-pulse programming.” Writing to the device can only be accomplished by addressing one register at a time. When taking one step, at least two registers are normally updated. Accordingly there must be a certain time delay between writing to the first and the second register. This programming necessity gives some special stepping advantages. Double-pulse Programming The normal way is to send two write pulses to the device, with the correct addressing in between, keeping the delay between the pulses as short as possible. Write signals will look as illustrated in figure12. The advantages are:

• low torque ripple
• correct step angles between each set of double pulses
• short compromise position between the two step pulses
• normal microstep resolution Single-pulse Programming A different approach is to send one pulse at a time with an equally-spaced duty cycle. This can easily be accom- plished and any two adjacent data will make up a microstep position. Write signals will look as in figure 13. The advantages are:
• higher microstep resolution
• smoother motion The disadvantages are:
• higher torque ripple
• compromise positions with almost- correct step angles This is the ideal solution for a system where there is an available micropro- cessor with extra capacity and low cost is more essential than simplicity. See typical application, figure 14. User Hints Never disconnect ICs or PC Boards when power is supplied. Choose a motor that is rated for the current you need to establish desired torque. A high supply voltage will gain better stepping performance even if the motor is not rated for the V MM voltage, the current regulation in PBL 3771/1 will take care of it. A normal stepper motor might give satisfactory result, but while microstepping, a “microstepping- adapted” motor is recommended. This type of motor has smoother motion due to two major differences, the stator / rotor teeth relationship is non-equal and the static torque is lower. The PBM 3960/1 can handle programs which generate microsteps at a desired resolution as well as quarter stepping, half stepping, full stepping, and wave drive. Fast or Slow Current Decay? There is a difference between static and dynamic operation of which the actual application must decide upon when to use fast or slow current decay. Generally slow decay is used when stepping at slow speeds. This will give the benefits of low current ripple in the drive stage, a precise and high overall average current, and normal current

SE-164 81 Kista-Stockholm, Sweden Telephone: +46 8 757 50 00 Specifications subject to change without notice. 1522-PBM 3960/1 Uen Rev. B © Ericsson Components AB 1999 Information given in this data sheet is believed to be accurate and reliable. However no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Ericsson Components. These products are sold only according to Ericsson Components' general conditions of sale, unless otherwise confirmed in writing.

Ordering Information

Package Part No. DIP Tube PBM 3960/1NS PLCC Tube PBM 3960/1QNS PLCC Tape & Reel PBM 3960/1QNT