PBL40215

PBL40215 ERICSSON | Alldatasheet

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Technical content

3-wire bus interface with optional hard wire lines. frequency discriminator and a preamble based data slicer. transmission is achieved by direct open loop modulation of the Tx VCO.

• High Tx output power to +7dBm
• Integrated PLL and high stability VCO´s
• 3-line serial interface bus
• Minimum 2.7 V supply voltage
• Low current consumption
• Differential Rx input and Tx output
• Flexible interface to various base- band controllers
• Exellent performance with Ericsson´s power amplifier PBL403 09
• Low cost Applications:
• DECT Handset and base station
• Wireless local area network ( WLAN )
• Wireless local loop ( WLL )

Figure 1. Block diagram. Figure 2. Package outlook.

Figure 3. DECT application. Figure 4. The European DECT band .

1.728 MHz

Frequency and time division. control info, data package and error control.

Figure 5. Pinning configuration. 1 EN Enable 3-wire interface and synthesiser.

2 REF PLL reference clock input

3V CC PLL Voltage supply to the frequency synthesiser. 4 GndPLL Ground connection to the frequency synthesiser. 5 GndCP Ground connection to the charge pump. CC CP Voltage supply to the charge pump.

Pin Descriptions (cont.): Pin number Name Function Schematic in/output of the pin

8 Not connected

9 Not connected

10 V CC VCO Voltage supply to the VCO

11 VTUNE Tuning voltage input for the VCO

12 GndVCO Ground connection to the VCO

13 GndFM Ground connection to the FM discriminator section. 14 DTX Tx data input for either analog or logic signal. 15 MOD Apply modulation. The PLL is set into open loop condition and modulation is applied to the VCO. 16 SHOLD Slice level hold logic input. (In Tx mode this input may also act as the MOD pin).

17 DRX Rx data output of FM discriminator for either analog

or logic signal.(In standby mode outputs lock detect) 18 DSL Data slice level output. 19 V CC FM Voltage supply to the FM discriminator section. 20 RSSI RSSI output of limiting strip detector chain. N/C Clamp to GndVCO VCC VCO VTUNE GndVCO A diode to GndCP and GndFM VCC FM DTX GndFM VCC FM MOD GndFM Bias VCC FM SHOLD GndFM Bias VCC FM DRX GndFM VCC FM DSL GndFM Clamp to GndFM 21 V CC RSSI Voltage supply to the RSSI section.

22 CAP+ External stabilising capacitors for limiting strip

DC input offset correction loop.

23 CAP-

Pin Descriptions (cont.): Pin number Name Function Schematic in/output of the pin 24 GndRSSI Ground connection to the RSSI. 25 PA Gate Output control signal for external PA power on/off.

26 IFIN- Rx IF inputs to internal channel filtering, limiting

amplifiers,RSSI and FM discriminator. Internally 27 IFIN+ matched to 300 Ω .

28 GndIF Ground connection to the down IF convertor and

channel filter sections.

29 V CC IF Voltage supply to the down IF convertor and

channel filter sections. 30 LD Lock detect. 31 IFOUT- Rx IF outputs to external adjacent channel filter. Internally matched to 300Ω .

32 IFOUT+

33, 36 GndRF Ground connection to the RF sections. 37, 40 34 RX- RF inputs to LNA and image reject mixer. 35 RX+ Internally matched to 100 Ω . 38 TX- Tx outputs to external PA. Internally matched to 39 TX+ 100 Ω . Each output requires an externalchoke to VCC . 41 V CC RF Voltage supply to the RF sections. 42 GATE Input to gate the Tx output power. 43 D Serial interface, Data . A diode to GndFM and GndIF VCC RF PA - Gate GndRF VCC IF IFIN-/IFIN+ both inputs alike GndIF A diode to GndFM and GndIF Clamp to GndIF VCC RF LD GndRF VCC RF IFOUT-/IFOUT+ both outputs alike GndRF A diode to GndIF and GndPLL VCC RF RX-/RX+ both inputs alike GndRF VCC RF TX-/TX+ Both inputs alike GndRF Clamp to GndRF VCC PLL GATE GndPLL Bias VCC PLL D GndPLL Bias

Pin Descriptions (cont.): Pin number Name Function Schematic in/output of the pin 44 CK Serial interface, Clock . 45 ST Serial interface, Strobe . 46 TXEN Transmitter enable. 47 DIE Gnd. pin used for internal shielding. Connected to DIE substrate.

48 RXEN Receiver enable

Figure 6. Block diagram. (a). Under continous operation and during power-up sequences. Every pin withstands the ESD test in accordance with MIL-STD-883 (method 3050) and IEC 68-2.

a. Time may depend upon settling time of the limiting strip DC correction feedback. b. Time for the receive or transmit gain to be within 1 dB of its final value. supply. The digital signals are EN, RXEN,TXEN, ST, D, CK, GATE, LD, MOD and SHOLD. Figure 7. Typical current consumtion.

The 3-Wire Control Bus Interface. The 3-wire serial bus interface controls the various IC parameters and consists of 3 lines, strobe, data and clock ( ST, D, CK ). Alternatively, selected power control modes may be controlled by 3 hard-wire control lines ( EN, RXEN, TXEN ). The 3-wire bus is active when either EN or ST, or both are active. The strobe signal is used to enable the clock and latch the data frame. Each frame consists of 24 bits, built from a word field and a data field. The word address is the last bit to be sent ( LSB ), with the data field being the proceeding 23 bits. Data on D is shifted into the frame register by clock CK. The 3-wire interface allows setting of word A and word B. These control the IC configuration. F0 W0 F1 D0 F2 D1 F3 D2 F4 D3 F5 D4 F6 D5 F7 D6 F8 D7 F9 D8 F10 D9 F11 D10 F12 D11 F13 D12 F14 D13 F15 D14 F16 D15 F17 D16 F18 D17 F19 D18 F20 D19 F21 D20 F22 D21 F23 D22 LSB Last in Word AddressData MSB First in Frame:

Description

tag: Frame definition: ST Digital input The control section is powered up when ST is low. Data is latched on the rising edge. ST has an internal 160kΩ pull up resistor to VCC PLL. CK Digital input 3-wire interface clock. May be running continuously, but to minimise the risk of VCO spurious it is recommended that the clock only runs when required. D Digital input 3-wire interface data. Data latched by rising edge of CK. EN Digital input IC enable control. Active low. The control section is powered when EN is active. EN has an internal 160 kΩ pull up resistor to V CC PLL. RXEN Digital input Receiver enable. Active low. TXEN Digital input Transmitter enable. Active low. Pin Spec. Description Digital Interface: Digital Interface: Parameter Condition Symbol Min. Typ. Max. Unit Serial clock frequency f CK 13.9 MHz Delay strobe to first rising clock t SCK 288 ns Data setup time: D to CK t DS 18 ns Data hold time t DH 18 ns Clock pulse widh high t CKW 18 ns Strobe hold time high t SW 144 ns

Figure 8. 3-wire timing diagram. Word A has the address W0 = 0. It permits IC operation and defines the synthesiser frequency. control section takes power. All configurations are erased and must be re-programmed if the chip has been disabled.

Data address Name Default Description D0 CE 0 0 = Chip disable 1 = Chip enable Active low on the external EN pin will also enable the chip D1 CL 0 0 = Internal control flags 1 = External control lines D2 CNT_A0 0 D3 CNT_A1 0 D4 CNT_A2 0 D5 CNT_A3 0 D6 CNT_A4 0 D7 CNT_M 0 Synthesiser frequency counter M 0 → M = 32 (used for receive) 1 → M = 34 (used for transmit) D8 CNT_R 0 Synthesiser reference counter R 0 → R = 6 used if REF = 10.368 MHz 1 → R = 8 used if REF = 13.824 MHz D9 (a) 0 D10 (a) 0 D11 RXVCO_EN 0 (1) D12 (a) 0 D13 (a) 0 D14 TXVCO_EN 0 (1) D15 Reserved 0 (a) D16 DRX_T 0 1 = Analog signal output at DRX pin. 0 = Digital data output at DRX pin. D17 TX_P0 0 D18 TX_P1 0 D19 RX_G 0 D20 IFT0 1 D21 IFT1 1 D22 IFT2 0 Receiver VCO enable . 000 = VCO disabled. Any other setting activates the VCO. (default 100) Transmit power trim bits 00 = -1.3 dB Min. 0 (LSB) to 1 (MSB) 01 = Nominal power 10 = +1.3 dB 11 = +1.9 dB Max. Synthesiser frequency counter A bit 0 (LSB) to 4 (MSB) IRRX gain. 0 = +0dB extra 1 = +9dB extra Demodulation IF frequency trim bits 0 (LSB) to 2 (MSB). This should be programmed to the default settings. a. Use ´0´ only. b. Recommended at all times. Word A Table. Transmit VCO enable . 000 = VCO disabled. Any other setting activates the VCO. (default 100)

Word B. Description. Word B has address W0 =1. It controls modes, functionality and configuration. Word B signals are only active when CE is enabled or EN is active. Data address Name Default Description D0 SYN_EN 0 1 = Synthesiser power on. 0 = Synthesiser power off. D1 IF_EN 0 1 = IF receiver enabled. IF mixer + RSSI + Demodulator + Slave PLL 0 = IF receiver disabled. D2 RX_EN 0 1 = Receiver power on. LNA + front end mixer 0 = Receiver power off. D3 TX_EN 0 1 = Transmit power on. 0 = Transmit power off. D4 SHOLD_P 0 1 = Slice hold pin SHOLD, active high. 0 = Slice hold pin SHOLD, active low. D5 SHOLD_EN 0 1 = Slice hold enable. 0 = Slice hold disable. Active level on the external SHOLD pin determined by SHOLD_P will also enable slice hold. D6 MOD_P 0 1 = Modulation pin MOD, active high. 0 = Modulation pin MOD, active low. D7 MOD_EN 0 1 = Enable modulation. 0 = Disable modulation. Active level on the external MOD pin determined by MOD_P will also enable modulation. D8 MOD_SW 0 1 = Modulation controlled by the SHOLD pin. 0 = Modulation controlled by the MOD pin. The effect is to multiplex between the MOD & SHOLD pins. D9 GATE_P 0 1 = TX gating pin, GATE active high. 0 = TX gating pin, GATE active low. D10 CPC0 0 Charge pump operation control. D11 CPC1 0 00 = Normal 01 = Force CP voltage down ( =VCO frequency up ) 11 = Tri-state 10 = Force CP voltage up ( =VCO frequency down ) D12 to D23 Reserved. These bits need not to be programmed. Word B Table.

a). See figure PA_GATE timing diagram. b). See figure SLICE control. Figure 9. Control logic.

Hard Wire Control Lines. The 3 hardwire control lines EN, RXEN and TXEN allow control of the IC by a controller with limited interface access or capabili- ties. Typically, controllers with only one access per slot or no access between slots. For correct operation the 3 hard wire lines require appropriate programming of the CE and CL flags. The hardwire lines directly force the state of the appropriate word B flags as detailed below. ƒ-φ PLL Modulator IF LO and Modulation Section. The LO section consists of a TX VCO with a frequency doubler, a RX VCO and a charge pump PLL. The VCO´s are fully integrated and are phase/frequency locked to an external reference frequency applied to the REF pin. The frequency is programmed by the 3-wire interface. Lock detect is available on the LD pin. When neither TX_EN or RX_EN are active, lock detect is also available at the DRX output. The RX VCO runs at twice the frequency. The frequency of the RX VCO is divided by 2 for the PLL. The TX VCO runs at half the TX frequency to improve pulling immunity to TX harmonics. A frequency doubler generates the TX LO for the PLL. The TX VCO is modulated by an external signal applied to the DTX pin. The DTX input is permanently connected to the TXVCO. An active MOD_EN signal disables the PLL charge pump output which allows modulation to be applied. A hardware modulation enable signal may be applied to either the MOD pin or SHOLD pin depending upon setting of the MOD_SW flag. Hard wire line Description EN Powers the serial bus interface. Upon the rising edge of ST and provided CL is set to 1, the effect is as SYN_EN. RXEN Provided EN is active and CL is set to 1, the effect is as IF_EN and RX_EN. TXEN Provided EN is active and CL is set to 1, the effect is as TX_EN.

TX VCO. A fully integrated balanced VCO. The VCO frequency is controlled by the voltage applied to the VTUNE pin, and the applied modulation voltage. Both have a negative sensitivity, i.e., as the voltage increases, the VCO frequency decreases. The base-band must invert the transit modulation data to allow for this. The tuning voltage is referenced to VCC VCO. The VCO is buffered to provide isolation against frequency pulling and reverse injection. TX VCO Table. Typical TX VCO analog modulation voltage table. Parameter Condition Symbol Min. Typ. Max. Unit Carrier frequency range 0.4 ≤VT≤VCC -0.4 ƒ C 940 967 MHz Tuning voltage V T 0.4 V CC -0.4 V Frequency tuning sensitivity ƒ SEN ~-40 ~-72 ~-140 MHz/V Frequency pulling stand-by ↔ RX ƒ PULL kHz stand-by ↔ TX Frequency pushing against V CC , CPC = 2 ƒ PUSH 1.5 MHz/V Frequency drift per slot of 417 µsƒ DRIFT 7.5 kHz Modulation pushing modulation deviation against V CC ƒMPUSH kHz/V Modulation tuning sensitivity modulation deviation against VT ƒMSEN kHz/V Analog modulation voltage (a) ± 144 kHz see table below V MOD ± 375 mVpk (a). The input analog signal is expected to vary between 0V and 0.75V Pre-modulation and post-modulation, it is expected to have a level of 0.375. Channel No Supply voltage Condition Symbol -20 °C2 0 °C7 0 °C Unit 0 V CC = 2.7 For ± 144 kHz V MOD27 239 ± 222 211 mVpk 31 223 ± 208 200 0V CC = 3.3 For ± 144 kHz V MOD33 370 ± 339 320 mVpk 31 344 ± 315 299 0V CC = 3.6 For ± 144 kHz V MOD36 460 ± 419 395 mVpk 31 426 ± 390 369

RX VCO Table. The PLL. N/N+1 ƒ-φ R M A Store REF LO CP LD LD & DRX 864kHz The frequency synthesiser is based on a charge pump PLL ( Phase Locked Loop ). Counter R divides the reference clock, REF. The division ratio, R, is determined by the value of CNT_R. Counters N, A and M form a modulus pulse swallow counter which divides the LO clock by M∗N+A . The value of M is determined by CNT_M. The value of A is taken from the CNT_A. A combined 3 state frequency-phase detector compares the divided REF and LO signals and controls the charge pump.The frequency-phase comparator outputs are controlled by the CPC1-0 bits and MOD_EN. The action of the CPC bits are unsynchronised. The action of MOD_EN is synchronised to the charge pump states, holding the charge pump in tri-state mode when MOD becomes active. An active high lock detect signal is provided when frequency lock has been achieved for 148 µs. The signal is available on the LD pin and on the DRX pin when SYN_EN is active and neither of RX_EN or TX_EN are active. The PLL is designed to work with two different reference frequencies, 10.368 MHz ( = 9 x the DECT bitrate of 1.152 MHz ) or 13.824 MHz ( = 12 x the DECT bitrate of 1.152 MHz ) RX VCO. A fully integrated balanced VCO. The VCO frequency is controlled by the voltage applied to the VTUNE pin, and has a negative sensitivity, i.e., as the voltage increases, the VCO frequency decreases. The tuning voltage is referenced to V CC VCO. The VCO is buffered to provide isolation against frequency pulling and reverse injection. A divider by 2 stage, reduces the VCO frequency by 2 for the PLL. Parameter Condition Symbol Min. Typ. Max. Unit Carrier frequency range 0.4 ≤VT≤VCC -0.4 ƒ C 3.53 3.65 GHz Tuning voltage V T 0.4 V CC -0.4 V Frequency sensitivity ƒ SEN ~-100 ~-280 ~-460 MHz/V Frequency pulling stand-by ↔ RX ƒ PULL kHz stand-by ↔ TX Frequency pushing against V CC , CPC = 2 ƒ PUSH 1,0 MHz/V Noise floor nominal output power N FLR -140 dBc/Hz

The synthesiser frequency is given by, fRF = (fREF / R) (M * N+A) where: f RF = RF frequency fREF = either 10.368 MHz or 13.824 MHz R = 6 or 8 (see CNT_R) M = 32 or 34 (see CNT_M) N = 32 PLL Table. Transmit section. TX GATE Description. The transmitter consists of a band-pass filter, a gated amplifier and a pre-power amplifier. The band-pass filter cleans the output signal of the LO modulator prior to amplification. The gated amplifier is controlled by the GATE pin, with signal polarity determined by the GATE_P flag. The attenuation of the gating amplifier should be used in addition to the external PA to meet the transmit power ramp requirements. An active GATE signal causes the output power to ramp up to its required power level. An inactive GATE signal causes the output power to ramp down to a leakage level. Spectral spreading requirements are best met if the external PA turns on before the power ramp up, and turn off after the power ramp down. Should the external PA be controlled by the same GATE signal, a delayed copy of the GATE signal is provided at the PA _GATE output. The TX output is balanced with an impedance of ~100 Ω and requires external inductors to V CC RF. The transmit power may be trimmed by the TX_P 0-1 bits. The TX is designed for easy interfacing to the PBL 403 09 DECT PA circuit, which is enabled with an active low signal. See application diagram for details. Parameter Condition Symbol Min. Typ. Max. Unit Carrier frequency range 0.4 ≤VT≤VCC -0.4 ƒ C 1769 1934 MHz Lock time (1) tLOCK 320 µs Charge pump current I CP 400 µA Charge pump leakage tri-state I LEAK 100 pA Reference frequency CNT_R=0 ƒ REF 10.368 MHz CNT_R=1 13.824 Reference input voltage V REF 50 mVpk (1). Depends upon charge pump loop components.

Figure 10. GATE / PA_GATE timing diagram, GATE_P = 0.

Image Reject Front End Table. The IF outputs are self biasing and define a balanced output impedance of 300 Ω . The output should be matched to an external adjacent channel filter. The gain is switchable to cater for the insertion loss of different external filters. Image Reject Front End. -π/4π/4 IR RX The image reject front end consists of an LNA (Low Noise Amplifier) with dual outputs, 2 mixers, quadrature LO generation, 2 low pass filters, a +π/4 and a -π/4 all-pass filters and a summing output stage. The receiver input is a 1.9 GHz LNA with a characteristic balanced input impedance. The inputs are self biassing and require external matching to the source, with DC blocking capacitors if the source passes DC. The high side image rejection mixer, down converts from RF to an IF frequency of 110.6 MHz. Parameter Condition Symbol Min. Typ. Max. Unit Input frequency range ƒ IN 1800 1890 2000 MHz Output frequency range ƒ OUT 100 110.6 120 MHz Gain 1 RX_G = 0 G1 18 20 22 dB Gain 2 RX_G = 1 G2 23 25 27 dB Input IP3 RX_G = 0 IP3 -21 -17 dBm RX_G = 1 -23 Input 1 dB compression RX_G = 0 CPI1 -24 dBm RX_G = 1 -31 Output 1 dB compression CPO1 -7 dBm Output saturation -1.5 dBm Lower image suppression Tested at ƒ IN -2•110.6 MHz SSB 29 35 dB Noise figure NF 3.6 4.1 dB Input impedance Z IN 100 Ω Output impedance Z OUT 300 Ω Input VSWR VSWR I 1.5:1 - Output VSWR VSWR O 1.5:1 -

RSSI, an FM discriminator, a post detection filter and a data slicer. The IF inputs are self biasing and have a balanced input impedance of 300 Ω . Matching to the external filter is required. A band-pass filter provides additional channel selection and noise filtering prior to the limiting chain. The quadrature based FM discriminator and post detection filter are self tuned to the required frequency by a slave PLL. a more accurate level from this signal. An external capacitor is required on the DSL pin. When the IF section is powered off, the DSL pin is tri-stated. Figure 11. Slice control.

Limiting Amplifier and RSSI ( Received Signal Strength Indicator ). The stage consists of a limiting amplifier chain with an RSSI detector. The inputs are internally coupled from the channel selection filter which limits the noise bandwidth. A balanced DC offset correction loop, provides maximum sensitivity, and ensures a short settling time upon power up. An RSSI output provides a voltage proportional to the logarithm of the rectified input level. The rise time response of the RSSI output and the peak hold is dependent upon the external circuit. Limiting Amplifier strip and RSSI, Table. Parameter Condition Symbol Min. Typ. Max. Unit Frequency range ƒ 11.7 MHz Limiter 1 dB bandwidth ƒ 1dB 22 MHz Voltage gain G 74 dB RSSI range R R 74 dB RSSI minimum detection level measured at IFIN RD MIN -83 dBm RSSI maximum detection level measured at IFIN RD MAX -9 dBm RSSI slope R SLOPE 15.2 mV/dB Zero scale RSSI output voltage VR ZERO 375 mVpk Full scale RSSI output voltage VR FULL 1500 mVpk RSSI relative error best fit to straight line (a) R ERR ±2.5 dB RSSI rise time 20 pF load t RISE 2 µs Feedback capacitance C CAP 18 nF a. The RSSI relative accuracy is the deviation of the RSSI value from a best fit straight line fitted to several calibration points. These points are determined for each part.

Specifications subject to change without notice. 1522-PBL 402 15 Uen Rev.A © Ericsson Microelectronics AB January 2001 Information given in this data sheet is believed to be accurate and reliable. However no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Ericsson Microelectronics AB. These products are sold only according to Ericsson Microelectronics AB's general conditions of sale, unless otherwise confirmed in writing. Ericsson Microelectronics AB S-164 81 Kista-Stockholm, Sweden Telephone: (08) 757 50 00 www.ericsson.se/microe DIM. mm inch A 1.60 0.063 A1 0.05 0.15 0.002 0.006 C 0.09 0.20 0.004 0.008 D 9.00 0.354 D1 7.00 0.276 D3 5.50 0.217 e 0.50 0.020 E 9.00 0.354 E1 7.00 0.276 E3 5.50 0.217 L1 1.00 0.039 K0 ∞(min.), 3.5°(typ.), 7∞(max.) TQFP 48 Pin Package