PBL386612

PBL38661-2 ERICSSON | Alldatasheet

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Description

The PBL 386 61/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated circuit for use in Central Office, MUX and other telecommunications equipment. The PBL 386 61/2 has been optimized for low total line interface cost and a high degree of flexibility in different applications. The PBL 386 61/2 emulates a transformer equivalent dc-feed, programmable between 2x25 Ω and 2x900 Ω , with short loop current limiting adjustable to max 65 mA. A second lower battery voltage may be connected to the device to reduce short loop power dissipation. The SLIC automatically switches between the two battery supply voltages without need for external components or external control. The SLIC incorporates loop current and ring trip detection functions. The PBL 386 61/2 is compatible with loop start signalling. Two- to four-wire and four- to two-wire voice frequency (vf) signal conversion is accomplished by the SLIC in conjunction with either a conventional CODEC/filter or with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable line terminating impedance could be complex or real to fit every market. Longitudinal line voltages are suppressed by a feedback loop in the SLIC and the longitudinal balance specifications meet Bellcore TR909 requirements. The PBL 386 61/2 package is 28-pin PLCC. Figure 1. Block diagram.

• Selectable overhead voltage principle – All adaptive: The overhead voltage follows 0.6 VPeak < signals < 6.2 VPeak. – Semi adaptive: The overhead voltage follows 3.1 VPeak < signals < 6.2 VPeak.
• Metering 2.2 Vrms.
• High and low battery with automatic switching
• Battery supply as low as -10 V
• Only +5 V in addition to GND and battery (VEE optional)
• 39 mW on-hook power dissipation in active state
• Long loop battery feed tracks V Bat for maximum line voltage
• 44 V open loop voltage @ -48 V battery feed
• Constant loop voltage for line leakage <5 mA
• On-hook transmission
• Full longitudinal current capability during on-hook
• Programmable loop & ring-trip detector threshold
• Analog temperature guard

Parameter Symbol Min Max Unit Temperature, Humidity Storage temperature range T Stg -55 +150 °C Operating temperature range T Amb -40 +110 °C Operating junction temperature range, Note 1 T J -40 +140 °C Power supply, 0°C ≤ TAmb ≤ +70°C VCC with respect to AGND V CC -0.4 6.5 V VEE with respect to AGND V EE VBat 0.4 V VBat with respect to BGND, continuous V Bat -75 0.4 V VBat with respect to BGND, 10 ms V Bat -80 0.4 V VBat2 with respect to A/BGND V Bat2 VBat2 0.4 V Power dissipation Continuous power dissipation at TAmb ≤ +70 °CP D 1.5 W Ground Voltage between AGND and BGND V G -5 VCC V Relay Driver Ring relay supply voltage BGND +13 V Ring relay current 75 mA Ring trip comparator Input voltage V DT , VDR VBat VCC V Input current I DT , IDR -5 5 mA Digital inputs, outputs (C1, C2, DET) Input voltage V ID -0.4 V CC V Output voltage (DET not active) V OD -0.4 V CC V Output current (DET) I OD 30 mA TIPX and RINGX terminals, 0°C < TAmb < +70°C, VBat = -50 V TIPX or RINGX current I TIPX, IRINGX -110 +110 mA TIPX or RINGX voltage, continuous (referenced to AGND), Note 2 V TA , VRA VBat 2V TIPX or RINGX, pulse < 10 ms, tRep > 10 s, Note 2 V TA , VRA VBat - 20 5 V TIPX or RINGX, pulse < 1 µs, tRep > 10 s, Note 2 V TA , VRA VBat - 40 10 V TIP or RING, pulse < 250 ns, tRep > 10 s, Note 3 V TA , VRA VBat - 70 15 V Recommended Operating Condition Parameter Symbol Min Max Unit Ambient temperature T Amb 0 +70 °C Maximum supplied VCC with respect to AGND V CC 4.75 5.25 V VEE with respect to AGND V EE VBat -4.75 V VBat with respect to BGND V Bat -58 -10 V VBat2 with respect to BGND V Bat2 VBat -10 V Notes 1. The circuit includes thermal protection. Operation above max. junction temperature may degrade device reliability. 2. A diode in series with the VBat input increases the permitted continuous voltage and pulse < 10 ms to -85 V. A pulse ≤1µs is increased to the greater of |-70V| and |VBat -40V|. 3. R F1 and RF2 ≥20 Ω are also required. Pulse is supplied to TIP and RING outside RF1 and RF2.

Four-wire to two-wire, g4-2 6 relative to 0 dBm, 1.0 kHz. EL = 0 V 0.3 kHz < f < 3.4 kHz -0.15 0.15 dB f = 8 kHz, 12 kHz, -1.0 -0.2 0 dB 16 kHz -1.0 -0.3 0 dB Four-wire to four-wire, g 4-4 6 relative to 0 dBm, 1.0 kHz. EL = 0 V 0.3 kHz < f < 3.4 kHz -0.15 0.15 dB Insertion loss Two-wire to four-wire, G2-4 6 0 dBm, 1.0 kHz, Note 5 VTXG 2-4 = 20 • Log ,E RX = 0VTR -6.22 -6.02 -5.82 dB Four-wire to two-wire, G4-2 6 0 dBm, 1.0 kHz, Notes 5, 6 VTRG 4-2 = 20 • Log ,E L = 0ERX -0.2 0.2 dB Gain tracking Two-wire to four-wire RLDC ≤ 2kΩ 6 Ref. -10 dBm, 1.0 kHz, Note 7 -40 dBm to +3 dBm -0.1 0.1 dB -55 dBm to -40 dBm -0.2 0.2 dB Four-wire to two-wire R LDC ≤ 2kΩ 6 Ref. -10 dBm, 1.0 kHz, Note 7 -40 dBm to +3 dBm -0.1 0.1 dB -55 dBm to -40 dBm -0.2 0.2 dB Noise Idle channel noise at two-wire C-message weighting 7 12 dBrnC (TIPX-RINGX) Psophometrical weighting -85 -78 dBmp Note 8 Harmonic distortion Two-wire to four-wire 6 0 dBm, 1.0 kHz test signal -50 dB Four-wire to two-wire 0.3 kHz < f < 3.4 kHz -50 dB Battery feed characteristics Constant loop current, I LConst 12 I LProg = 500 R LC 18 < ILProg < 65 mA 0.92 I LProg ILProg 1.08 ILProg mA Ref Parameter fig Conditions Min Typ Max Unit Figure 6. Frequency response, insertion loss, gain tracking. 1 << RL, RL = 600 Ωω C R T = 120 kΩ , RRX = 120 kΩ PBL 386 61/2 TIPX RINGX RSN VTX R T R RX E RX R L VTR ILDC C E L VTX

Programmable threshold, IDET ILTh = 500 0.9•I LTh ILTh 1.1•ILTh mA RLD Ring trip comparator Offset voltage, ∆V DTDR Source resistance, RS = 0 Ω -20 0 20 mV Input bias current, IB IB = (IDT + IDR )/2 -50 -20 200 nA Input common mode range, VDT , VDR VBat+1 -1 V Ring relay driver Saturation voltage, VOL IOL = 50 mA 0.5 V Off state leakage current, ILk VOH = 12 V 100 µA Digital inputs (C1, C2, C3) Input low voltage, VIL 0 0.5 V Input high voltage, VIH 2.5 V CC V Input low current, IIL VIL = 0.5 -200 µA Input high current, IIH VIH = 2.5 V 200 µA Detector output (DET) Output low current, IOL VOL < 0.6V 0.5 1 mA Internal pull-up resistor 10 k Ω Power dissipation (VBat = -48V, VBat2 = -32V) P1 Open circuit state, C1, C2, C3 = 0, 0, 0 14 mW P2 @ VEE = -5V Active state, C1, C2, C3 = 0, 1, 0 39 mW P3 @ VEE = -48V Longitudinal current = 0 mA, I L = 0 mA 44 mW P4 @ VEE = -5V R L = 300Ω (off-hook) 710 mW P5 @ VEE = -5V R L = 800Ω (off-hook) 340 mW Power supply currents (VBat = -48V) VCC current, ICC Open circuit state 0.8 mA VEE current, IEE C1, C2, C3 = 0, 0, 0 -0.1 mA VBat current, IBat -0.2 mA VCC current, ICC Active state 2.0 mA VEE current, IEE C1, C2, C3 = 0, 1, 0 0.1 mA VBat current, IBat On-hook, Long Current = 0 mA, IL = 0 mA -0.7 mA Power supply rejection ratios VCC to 2- or 4-wire port Active State 28.5 35 dB VEE to 2- or 4-wire port C1, C2, C3 = 0, 1, 0 28.5 55 dB VBat to 2- or 4-wire port 50 Hz < f< 3400 Hz, V n = 100mV 28.5 40 dB VBat2 to 2- or 4-wire port 28.5 60 dB Temperature guard Junction threshold temperature, TJG 140 °C Parameter fig Conditions Min Typ Max Unit Ref

1. The overload level is automatically expanded when the signal level > 3.1 VPeak and is specified at the two-wire port with the signal source at the four-wire receive port. 2. The two-wire impedance is programmable by selection of external component values according to: ZTR = ZT/|G2-4S α RSN | where: ZTR = impedance between the TIPX and RINGX terminals ZT = programming network between the VTX and RSN terminals G 2-4S = transmit gain, nominally = -0.5 α RSN = receive current gain, nominally = 400 (current defined as positive flowing into the receivesumm- ing node, RSN, and when flowing from tip to ring). 3. Higher return loss values can be achieved by adding a reactive component to R T, the two-wire terminating impedance programming resistance, e.g. by dividing RT into two equal halves and connecting a capacitor from the common point to ground. 4. The overload level is automatically expanded as needed up to 3.1 V Peak when the signal level >1.55 VPeak and is specified at the four-wire transmit port, VTX , with the signal source at the two-wire port. Note that the gain from the two-wire port to the four-wire transmit port is G 2-4S = -0.5. 5. Secondary protection resistors RF impact the insertion loss as explained in the text, section Transmission. The specified insertion loss is for R F = 0. 6. The specified insertion loss tolerance does not include errors caused by external components. 7. The level is specified at the four-wire receive port and referenced to a 600 Ω programmed two-wire impedance level. 8. The two-wire idle noise is specified with the four-wire receive port grounded (ERX = 0; see figure 6). The four-wire idle noise at VTX is the two-wire value -6 dB and is specified with the two-wire port terminated in 600 Ω L). The noise specification is referenced to a 600 Ω programmed two-wire impedance level at VTX. The four- wire receive port is grounded (E RX = 0).

Refer to figure 7. PLCC Symbol Description 1 VBAT Battery supply voltage. Negative with respect to BGND. 2 VBAT2 An optional second battery voltage, connected in series with a diode, or an external powerhandling resistor connects to this pin. 3 AOV A daptive O verhead Voltage. If the pin is left open then the overhead voltage is set internally to 3.1 VPeak in off-hook and 1.4 VPeak in on-hook. The overhead voltage will adapt to signals > 3.1 VPeak. If the pin is connected to AGND then no internal overhead voltage is set. The overhead voltage adapts to 0.6 VPeak < signals < 6.2 VPeak. 4 PSG Programmable Saturation G uard. The resistive part of the DC feed characteristic is programmed by a resistor connected from this pin to VBAT. 5 LP Low Pass saturation guard filter capacitor connected here to filter out noise and improve PSRR. Other end of CLP connects to VBAT. 6 DT Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic level low, indicating off-hook condition. The ring trip network connects to this input. 7 DR Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic level low, indicating off-hook condition. The ring trip network connects to this input. 8 VEE -5V to VBAT power supply. 9 REF A 15 k Ω resistor should be connected between this pin and AGND. 10 NU N ot U sed. Must be left open. 11 PLC Prog. Line C urrent, the constant current part of the DC feed characteristic is programmed by a resistor connected from this pin to AGND. 12 PLD Programmable Loop D etector threshold. The loop detection threshold is programmed by a resistor connected from this pin to AGND. 13 VCC +5 V power supply. 14 NU N ot U sed. Pin must be connected to AGND. 15 C2 C1 and C2 are digital inputs C ontrolling the SLIC operating states. Refer to 16 C1 section operating states for details. 17 NC N o C onnect. Must be left open. 18 DET Detector output. Active low when indicating loop or ring trip detection, active high when indicating ground key detection 19 RSN R eceive Summing N ode. 400 times the current flowing into this pin equals the metallic (transversal) current flowing from RINGX to TIPX. Programming networks for two-wire impedance and receive gain connect to the receive summing node. 20 AGND A nalog G round, should be tied together with BGND. 21 VTX Transmit vf output. The ac voltage difference between TIPX and RINGX, the ac metallic voltage, is reproduced as an unbalanced GND referenced signal at VTX with a gain of -0.5. The two-wire impedance programming network connects between VTX and RSN. 22 RRLY R ing R elay driver output. 23 TS Tip Sense should be connected to TIPX. 24 NC N o C onnect. Must be left open.

25 HP H igh Pass connection for ac/dc separation capacitor C

HP . Other end of CHP connects to RINGX (pin 26). 26 RINGX The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage protection components and ring relay (and optional test relay). 27 BGND B attery G round, should be tied together with AGND. 28 TIPX The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage protection components and ring relay (and optional test relay).

Figure 7. Pin configuration 28 pin PLCC package, top view. Table 1. SLIC operating states.

Figure 9. Simplified ac transmission circuit. L is the ac metallic current. the 0 - 20kHz frequency range. RX controls four- to two-wire gain.

Figure 10. Hybrid function. in conventional CODEC/filter combinations.

• α RSN ZT G2-4S • ( ZL + 2RF) When choosing RTX , make sure the output load of the VTX terminal (RTX //RT in figure 12) is > 20 kΩ . If calculation of the ZB formula above yields a balance network containing an inductor, an alternate method is recom- mended. Contact Ericsson Microelectron- ics for assistance. The PBL 386 61/2 SLIC may also be used together with programmable CODEC/ filters. The programmable CODEC/filter allows for system controller adjustment of hybrid balance to accommodate different line impedances without change of hard- ware. In addition, the transmit and receive gain may be adjusted. Please, refer to the programmable CODEC/filter data sheets for design information. Longitudinal Impedance A feed back loop counteracts longitudinal voltages at the two-wire port by injecting longitudinal currents in opposing phase. Thus longitudinal disturbances will ap- pear as longitudinal currents and the TIPX and RINGX terminals will experience very small longitudinal voltage excursions, leav- ing metallic voltages well within the SLIC common mode range. The SLIC longitudinal impedance per wire, Z LoT and ZLoR , appears as typically 20 Ω to longitudinal disturbances. It should be not- ed that longitudinal currents may exceed the dc loop current without disturbing the vf transmission. Capacitors C TC and CRC If RFI filtering is needed, the capacitors designated CTC and CRC in figure 12, con- nected between TIPX and ground as well as between RINGX and ground, may be mounted. C TC and CRC work as RFI filters in con- junction with suitable series impedances (i.e. resistances, inductances). Resistors R F1 and RF2 may be sufficient, but series inductances can be added to form a sec- ond order filter. Current-compensated in- ductors are suitable since they suppress common-mode signals with minimum influ- ence on return loss. Recommended values for C TC and CRC are below 1 nF. Lower values impose smaller degradation on re- turn loss and longitudinal balance, but also attenuate radio frequencies to a smaller extent. The influence on the impedance loop must also be taken into consideration when programming the CODEC. C TC and C RC contribute to a metallic impedance of 1/(π•f•C TC ) = 1/(π•f•C RC ), a TIPX to ground impedance of 1/(2•π•f•C TC ) and a RINGX to ground impedance of 1/(2•π•f•C RC ). AC - DC Separation Capacitor, CHP The high pass filter capacitor connected between terminals HP and RINGXpro- vides the separation of the ac and dc signals. C HP positions the low end frequen- cy response break point of the ac loop in the SLIC. Refer to table 1 for recommended value of C HP . Example: A CHP value of 68 nF will position the low end frequency response 3dB break point of the ac loop at 13 Hz (f 3dB) according to f3dB = 1/(2•π•R HP •C HP ) where R HP = 180 kΩ .

Figure 11. The AOV funktion when the AOV-pin is left open. (Observe, burst that may occur with DTMF signaling. Table 1. RSG , CLP and CHP values for different feeding characteristics. different feeding characteristics. (references A-C in figure 13). (references D in figure 13). from the linecurrent reduction).

2 SLIC will emulate constant current feed

(references A-C in figure 13).

• 25 Ω 12 and 2•900 Ω (references D in figure 13). The current limitation region is adjustable between 0 mA and 65 mA 13. When the line current is approaching open loop conditions, the overhead volt- age is reduced. To ensure maximum open loop voltage, even with telephone line leak- age, this occurs at a line current of approx- imately 5 mA (references E in figure 13). After the overhead voltage reduction, the line voltage is kept nearly constant with a steep slope corresponding to 2
• 25 Ω (ref- erence G in figure 13). The open loop voltage, VTRMax , measured between the TIPX and RINGX terminals is tracking the battery voltage V Bat (referenc- es H in figure 13). VTRMax is programmable by connecting the AOV-pin to AGND or by

Refer to table 2 for typical VBOH values. Table 2. The battery overhead voltages even if the first battery voltage disappears. er dissipation outside the chip. bances from the metering puls generator. DET, to a logic low level when selected.

Detector Output (DET) The PBL 386 61/2 SLIC incorporates a detector output driver designed as open collector (npn) with a current sinking capa- bility of min 3 mA, and a 5 kΩ pull-up resistor. The emitter of the drive transistor is connected to AGND. A LED can be connected in series with a resistor (≈1 kΩ ) at the DET output to visualize, for example loop status. Relay driver The PBL 386 61/2 SLIC incorporates a ring relay driver designed as open collector (npn) with a current sinking capability of 50 mA.The emitter of the drive transistor is connected to BGND. The relay driver has an internal zener diode clamp to protect the SLIC from inductive kick-back voltages. No external clamp is needed. Control Inputs The PBL 386 61/2 SLIC has two digital control inputs, C1 and C2. A decoder in the SLIC interprets the con- trol input condition and sets up the com- manded operating state. C1 and C2 are internal pull-up inputs. Open Circuit State In the Open Circuit State the TIPX and RINGX line drive amplifiers as well as other circuit blocks are powered down. This caus- es the SLIC to present a high impedance to the line. Power dissipation is at a minimum and no detectors are active. Ringing State In the ringing state the SLIC will behave as in the active state with the exception that the ring relay driver and the ring trip detector are activated. The ring trip detec- tor will indicate off hook with a logic low level at the detector output. Active State TIPX is the terminal closest to ground and sources loop current while RINGX is the more negative terminal and sinks loop cur- rent. The loop current or the ground key detector is activated. The loop current de- tector indicates off hook with a logic low level and the ground key detector indicates active ground key with a logic high level present at the detector output. Overvoltage Protection PBL 386 61/2 must be protected against overvoltages on the telephone line. The overvoltages could be caused for instance by lightning, ac power contact and induc- tion. Refer to Maximum Ratings, TIPX and RINGX terminals, for maximum continu- ous and transient voltages. Secondary Protection The circuit shown in figure 12 utilizes series resistors together with a programmable overvoltage protector (e g Power Innova- tions TISP PBL1 or PBL2), serving as a secondary protection. The TISP PBLx is a dual forward-con- ducting buffered p-gate overvoltage pro- tector. The protector gate references the protection (clamping) voltage to negative supply voltage (i.e. the battery voltage, V B). As the protection voltage will track the negative supply voltage the overvoltage stress on the SLIC is minimised. Positive overvoltages are clamped to ground by a diode. Negative overvoltages are initially clamped close to the SLIC neg- ative supply rail voltage and the protector will crowbar into a low voltage on-state condition, by firing an internal thyristor. A gate decoupling capacitor, C GG , is need- ed to carry enough charge to supply a high enough current to quickly turn on the thyr- istor in the protector. C GG should be placed close to the overvoltage protection device. Without the capacitor even the low induct- ance in the track to the V B supply will limit the current and delay the activation of the thyristor clamp. The programmed line current, I LProg, must be less than 55 mA when using the TISP PBL1 to ensure that the TISP holding cur- rent is not exceeded. For higher pro- grammed line currents, the TISP PBL2 is recommended. The fuse resistors R F serve the dual pur- poses of being non- destructive energy dissipators, when transients are clamped and of being fuses, when the line is ex- posed to a power cross. Note that it is always important to use resistors not sensitive to temperature in series with PTC´s since the PTC acts as a capacitance for transients. Otherwise the SLIC is not protected properly.

Figure 13. Battery feed characteristics (without the protection resistors on the line). before all other power supply voltages. rounding the RSN pin is advisable. guardring connected to AGND. be short and very close to each other.

Note 11. 3.1 VPeak if AOV-pin is left open and 0.6 VPeak if AOV-pin is connected to AGND. Note 12. R Feed lower than 2x50Ω will reduce noise and PSRR performance in resistive loop region (reference D in figure 13). Better PSRR performance can be achieved by increasing C LP and CHP . Note 13. If the momentary value of the current in TIPX-pin or RINGX-pin exceeds 85mA harmonic distortion specification can be derated. Note 14. The accurate equation for RLC is: R LC = 500 - 10.4 • In (ILProg • 32) ILProg ILProg Note 15. 6.0V when AOV-pin is not connected, 3.9V when AOV-pin is connected to AGND. Note 16. 2.2VRMS if AOV-pin is left open and 0.4VRMS if AOV-pin is connected to AGND. Note 17. 6.8V when AOV-pin is left open, 4.2V when AOV-pin is connected to AGND.

Information given in this data sheet is believed to be accurate and reliable. However no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Ericsson Microelectronics AB. These products are sold only according to Ericsson Microelectronics general conditions of sale, unless otherwise confirmed in writing. Specifications subject to change without notice. 1522-PBL 386 61/2 Uen Rev.2A © Ericsson Microelectronics AB, 2000 This product is an original Ericsson product protected by US, European and other patents. Ericsson Microelectronics AB SE-164 81 Kista-Stockholm, Sweden Telephone: +46 8 757 50 00

Ordering Information

Package Temp. Range Part No. 28pin PLCC Tube 0 °C - + 70 °C PBL 386 61/2QNS 28pin PLCC Tape & Reel 0 °C - + 70 °C PBL 386 61/2QNT