PBL38650-2 ERICSSON | Alldatasheet

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Description

The PBL 386 50/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated circuit for use in Central Office Metering applications and other telecommunications equipment. The PBL 386 50/2 has been optimized for low total line interface cost and a high degree of flexibility in different applications. The PBL 386 50/2 emulates resistive loop feed, programmable between 2x50 Ω and 2x900 Ω , with short loop current limiting adjustable to max 45 mA. In the current limited region the loop feed is nearly constant current with a slight slope corresponding to 2x30kΩ . A second, lower battery voltage may be connected to the device to reduce short loop power dissipation. The SLIC automatically switches between the two battery supply voltages without need for external components or external control. The SLIC incorporates loop current, ground key and ring trip detection functions. The PBL 386 50/2 is compatible with both loop and ground start signaling. Two- to four-wire and four- to two-wire voice frequency (VF) signal conversion is accomplished by the SLIC in conjunction with either a conventional CODEC/filter or with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable two-wire impedance, complex or real, is set by a simple external network. Longitudinal voltages are suppressed by a feedback loop in the SLIC and the longitudinal balance specifications meet Bellcore TR909 requirements. The PBL 386 50/2 package options are 24-pin SSOP, 24-pin SOIC or 28-pin PLCC. Figure 1. Block diagram.

  • 24-pin SSOP package
  • Programmable two-wire signal headroom for 2.2 Vrms metering
  • High and low battery with automatic switching
  • Only +5 V feed in addition to battery
  • Selectable transmit gain (0.5x or 0.25x)
  • 70 mW on-hook power dissipation in active state
  • On-hook transmission
  • Long loop battery feed tracks Vbat for maximum line voltage
  • No power-up sequence
  • 43V open loop voltage @ -48V battery feed
  • Constant loop voltage for line leakage <5 mA (RLeak ~ >10 kΩ @ -48V)
  • Full longitudinal current capability during on-hook state
  • Analog over temperature protection permits transmission while the protection circuit is active
  • Line voltage measurement
  • Polarity reversal
  • Ground key detector
  • Tip open state with ring ground detector 24-pin SOIC, 24-pin SSOP, 28-pin PLCC RRL Y DET PSG REF LP PLD PLC VTX RSN PTG BGND AGND VBAT VBAT2 VCC HP RINGX TIPX DR DT Ring Relay Driver Input Decoder and Control Ring Trip Comparator Ground Key Detector Line Feed Controller and Longitudinal Signal Suppression Off-hook Detector VF Signal Transmission Two-wire Interface POV PBL 386 50/2 PBL 386 50/2 PBL 386 50/2

Parameter Symbol Min Max Unit Temperature, Humidity Storage temperature range T Stg -55 +150 °C Operating temperature range T Amb -40 +110 °C Operating junction temperature range, Note 1 T J -40 +140 °C Power supply, 0°C ≤ TAmb ≤ -70°C VCC with respect to A/BGND V CC -0.4 6.5 V VBat2 with respect to A/BGND V Bat2 VBat 0.4 V VBat with respect to A/BGND, continuous V Bat -75 0.4 V VBat with respect to A/BGND, 10 ms V Bat -80 0.4 V Power dissipation Continuous power dissipation at TAmb ≤ +70 °CP D 1.5 W Ground Voltage between AGND and BGND V G -0,3 0,3 V Relay Driver Ring relay supply voltage BGND+14 V Ring trip comparator Input voltage V DT , VDR VBat AGND V Input current I DT , IDR -5 5 mA Digital inputs, outputs (C1, C2, C3, DET) Input voltage V ID -0.4 V CC V Output voltage V OD -0.4 V CC V TIPX and RINGX terminals, 0°C < TAmb < +70°C, VBat = -50V Maximum supplied TIPX or RINGX current I TIPX, IRINGX -100 +100 mA TIPX or RINGX voltage, continuous (referenced to AGND), Note 2 V TA , VRA -80 2 V TIPX or RINGX, pulse < 10 ms, tRep > 10 s, Note 2 V TA , VRA VBat -10 5 V TIPX or RINGX, pulse < 1 µs, tRep > 10 s, Note 2 V TA , VRA VBat -25 10 V TIPX or RINGX, pulse < 250 ns, tRep > 10 s, Notes 2 & 3 V TA , VRA VBat -35 15 V Recommended Operating Condition Parameter Symbol Min Max Unit Ambient temperature T Amb 0 +70 °C VCC with respect to AGND V CC 4.75 5.25 V VBat with respect to AGND V Bat -65 -8 V AGND with respect to BGND V G -100 100 mV Notes 1. The circuit includes thermal protection. Operation at or above 140°C junction temperature may degrade device reliability. 2. With the diodes DVB and DVB2 included, see figure 12. 3. R F1 and RF2 ≥ 20 Ω is also required. Pulse is applied to TIP and RING outside RF1 and RF2.

Four-wire to two-wire, g4-2 6 relative to 0 dBm, 1.0 kHz. EL=0 V 0.3 kHz < f < 3.4 kHz -0.2 0.1 dB f = 8 kHz, 12 kHz, -1.0 0 dB 16 kHz -2.0 0 dB Four-wire to four-wire, g 4-4 6 relative to 0 dBm, 1.0 kHz, EL=0 V 0.3 kHz < f < 3.4 kHz -0.2 0.1 dB Insertion loss Two-wire to four-wire, G2-4 6 0 dBm, 1.0 kHz, Note 5 VTXG 2-4 = 20 · Log ; ERX = 0 -6.22 -6.02 -5.82 dB VTR PTG = AGND -12.24 -12.04 -11.84 dB Four-wire to two-wire, G4-2 6 0 dBm, 1.0 kHz, Note 6 VTRG 4-2 = 20 · Log ; EL = 0 -0.2 0.2 dB ERX Gain tracking Two-wire to four-wire 6 Ref. -10 dBm, 1.0 kHz, Note 7 -40 dBm to +3 dBm -0.1 0.1 dB -55 dBm to -40 dBm -0.2 0.2 dB Four-wire to two-wire 6 Ref. -10 dBm, 1.0 kHz, -40 dBm to +3 dBm -0.1 0.1 dB -55 dBm to -40 dBm -0.2 0.2 dB Noise Idle channel noise at two-wire C-message weighting, 2 wire 12 dBrnC (TIPX-RINGX) or four-wire (VTX) output Psophometrical weighting, 2 wire -78 dBmp C-message weighting, 4 wire 6 dBrnC Psophometrical weighting, 4 wire -84 dBmp Note 8 Harmonic distortion Two-wire to four-wire 6 0 dBm -67 -50 dB Four-wire to two-wire 0.3 kHz < f < 3.4 kHz -67 -50 dB Battery feed characteristics Loop current, I L , in the current 13 18mA ≤ IL ≤ 45 mA 0.92 I L IL 1.08 IL mA limited region, reference A, B & C Tip open state TIPX current, ILeak 7 S = closed; R = 7 kΩ , Note 10 -150 µA Tip open state RINGX current, ILRTo R LRTo = 0Ω , VBat = -48V I L mA R LRTo = 2.5 kΩ , VBat = -48V 17 mA Tip open state RINGX voltage, VRTo ILRTo < 23 mA V Bat +6 V Ref Parameter fig Conditions Min Typ Max Unit Figure 6. Frequency response, insertion loss, gain tracking. 1 << RL, RL = 600 Ωω C R T = 60 kΩ , RRX = 60 kΩ PBL 386 50/2 TIPX RINGX RSN VTX R T R RX E RX R L VTR ILDC C E L VTX

Tip voltage (ground start) 7 Active state, Tip lead open (S open), -4 -2.2 V Ring lead to ground through 150 Ω Tip voltage (ground start) Active state, tip lead to -48 V -6 -2.4 V through 7 kΩ (S closed), Ring lead to ground through 150 Ω Open circuit state loop current, ILOC R L = 0Ω -100 0 100 µA Loop current detector Programmable threshold, I LTh,I LTh = 500 0.85·ILTh ILTh 1.15·ILTh mA active, active reverse R LD R LD in kΩ , ILTh ≥ 7 mA Tip open state ILTh = 500 0.85·I LTh ILTh 1.15·ILTh mA R LD Ground key detector Ground key detector threshold (ILTIPX and ILRINGX difference to trigger ground key det.) 10 16 22 mA Line voltage measurement Pulse width, t LVM Note 9 5.5 µs/V Ring trip comparator Offset voltage, ∆V DTDR Source resistance, RS = 0 Ω -20 0 20 mV Input bias current, IB IB = (IDT + IDR )/2 -200 -20 200 nA Input common mode range, VDT , VDR VBat+1 -1 V Ring relay driver Saturation voltage, V OL IOL = 50 mA 0.2 0.5 V Off state leakage current, ILk VOH = 12 V 10 µA Digital inputs (C1, C2, C3) Input low voltage, VIL 0 0.5 V Input high voltage, VIH 2.5 V CC V Input low current, IIL VIL = 0.5 -50 µA Input high current, IIH VIH = 2.5 V 50 µA Detector output (DET) Output low voltage I OL = 0.5 mA 0.7 V Internal pull-up resistor 15 k Ω Power dissipation (VBat = -48V, VBat2 = -32V) P1 Open circuit state, C1, C2, C3 = 0, 0, 0 10 15 mW Active state, C1, C2, C3 = 0, 1, 0 P

2 Longitudinal current = 0 mA, I L=0 mA (on-hook) 70 85 mW

P3 R L = 300 Ω (off-hook) 730 mW P4 R L = 800 Ω (off-hook) 360 mW Power supply currents (VBat = -48V) VCC current, ICC Open circuit state 1.2 2.0 mA VBat current, IBat -0.1 -0.05 mA VCC current, ICC Active state 2.8 4.0 mA VBat current, IBat On-hook, Long Current = 0 mA -1.5 -1.1 mA Power supply rejection ratios V CC to 2- or 4-wire port Active State 30 42 dB VBat to 2- or 4-wire port f = 1 kHz V n = 100mV 36 45 dB VBat2 to 2- or 4-wire port 40 60 dB Temperature guard Junction threshold temperature, TJG 145 °C Thermal resistance 28-pin PLCC, θJP28plcc 39 °C/W 24-pin SOIC, θJP24soic 43 °C/W 24-pin SSOP, θJP24ssop 55 °C/W Parameter fig Conditions Min Typ Max Unit Ref

  1. The overhead voltage can be adjusted with the ROV resistor
  2. The two-wire impedance is programmable by selection of

ing node, RSN, and when flowing from ring to tip).

  1. Higher return loss values can be achieved by adding a
  2. The overhead voltage can be adjusted with the ROV
  3. Pin PTG = Open sets transmit gain to nom. -6.02dB

Transmission. The specified insertion loss is for RF = RP = 0.

  1. The specified insertion loss tolerance does not include

errors caused by external components.

  1. The level is specified at the two-wire port.
  2. The two-wire idle noise is specified with the port

port grounded (ERX = 0; see figure 6).

  1. Previous state must be active - loop or ground key
  2. If |VBExt| ≥ |VBat + 2 V|, where VBat is the voltage at VBAT pin,

the current ILeak is limited to ≈ 5mA. Figure 7. Tipx voltage.

Figure 8. Pin configuration, 24-pin SSOP, 24-pin SOIC and 28 pin PLCC package, top view. 2 RRLY R ing R elay driver output. The relay coil may be connected to maximum +14V. 3 HP Connection for H igh Pass filter capacitor, CHP . Other end of CHP connects to TIPX. protection components and ring relay (and optional test relay). 6 BGND B attery G round, should be tied together with AGND. protection components and ring relay (and optional test relay). 8 VBAT Battery supply Voltage. Negative with respect to AGND. 9 VBAT2 An optional second (2) Battery Voltage connects to this pin. resistor connected from this pin to VBAT.

11 NC N o internal C onnection

12 LP Connection for Low Pass filter capacitor, CLP. Other end of CLP connects to VBAT. low, indicating off-hook condition. The external ring trip network connects to this input. level low, indicating off-hook condition. The external ring trip network connects to this input.

19 NC N o internal C onnection

connected from this pin to AGND. voltage can be set to higher values. 24 REF A Reference, 49.9 kΩ , resistor should be connected from this pin to AGND.

25 NC N o internal C onnection

connect to the receive summing node. A resistor should be connected from this pin to AGND. 27 AGND Analog Ground, should be tied together with BGND. reproduced as an unbalanced GND referenced signal at VTX with a gain of 0.5 (or 0.25, see pin PTG). The two-wire impedance programming network connects between VTX and RSN.

0000 Open circuit -

1001 Ringing state Ring trip detector (active low)

2010 Active state Loop detector (active low)

3011 Active state Line voltage measurement (note 9)

4100 Tip open state Loop detector (active low)

5101 Active state Ground key detector (active high)

6110 Active reverse Loop detector (active low)

7111 Active reverse Ground key detector (active high)

Table 1. SLIC operating states.

combinations. Please, refer to figure 10. output load of the VTX terminal is >20kΩ . IL is the ac metallic current. RX controls four- to two-wire gain. to metallic loop current gain = 200. Figure 9. Simplified ac transmission circuit.

two wire side at sub-audio frequencies. Table 1. RSG , CLP and CHP values for different feeding characteristics. Figure 10. Hybrid function. within the SLIC common mode range. disturbing the vf transmission. and ground, can be used for RFI filtering.

Figure 12. Single-channel subscriber line interface with PBL 386 50/2 and combination CODEC/filter.

6.4 VPeak is maximum also for the 2-wire

12.8 VPeak on the 2-wire side can be han-

  1. Decide what overhead voltage(V
  2. In figure 11 the corresponding ROV for

the decided VTRO can be found.

  1. If the overhead voltage exceeds

6.4 VPeak , the G2-4S gain has to be

cally when the temperature drops.

  1. RP1 and RP2 may be omitted if DVB is in
  2. It is required to connect DHP between

terminal HP and ground if CHP >47nF.

Figure 13. Battery feed characteristics (without the protection resistors on the line). ringing source to tip and ring.

Ordering Information

Package Temp. Range Part No. 24 pin SSOP Tape & Reel 0° - +70° C PBL 386 50/2SHT 24 pin SOIC Tube 0 ° - +70° C PBL 386 50/2SOS 24 pin SOIC Tape & Reel 0° - +70° C PBL 386 50/2SOT 28 pin PLCC Tube 0 ° - +70° C PBL 386 50/2QNS 28 pin PLCC Tape & Reel 0° - +70° C PBL 386 50/2QNT Information given in this data sheet is believed to be accurate and reliable. However no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Ericsson Microelectronics. These products are sold only according to Ericsson Microelectronics' general conditions of sale, unless otherwise confirmed in writing. Specifications subject to change without notice. 1522-PBL 386 50/2 Uen Rev. A © Ericsson Microelectronics AB 1999 Ericsson Microelectronics AB SE-164 81 Kista-Stockholm, Sweden Telephone: +46 8 757 50 00 This product is an original Ericsson product protected by US, European and other patents. The TISPPBL2 is a dual forward- conducting buffered p-gate overvoltage protector. The protector gate references the protection (clamping) voltage to negative supply voltage (i e the battery voltage, V B ). As the protection voltage will track the negative supply voltage the overvoltage stress on the SLIC is minimized. Positive overvoltages are clamped to ground by a diode. Negative overvoltages are initially clamped close to the SLIC negative supply rail voltage and the protector will crowbar into a low voltage on-state condition, by firing an internal thyristor. A gate decoupling capacitor, C GG , is needed to carry enough charge to supply a high enough current to quickly turn on the thyristor in the protector. C GG shall be placed close to the overvoltage protection device. Without the capacitor even the low inductance in the track to the V Bat supply will limit the current and delay the activation of the thyristor clamp. The fuse resistors R F serve the dual purposes of being non- destructive energy dissipators, when transients are clamped and of being fuses, when the line is exposed to a power cross. If a PTC is choosen for R F, note that it is important to always use PTC´s in series with resistors not sensitive to temperature, as the PTC will act as a capacitance for fast transients and therefore will not protect the SLIC. Power-up Sequence No special power-up sequence is necessary except that ground has to be present before all power supply voltages. Printed Circuit Board Layout Care in PCB layout is essential for proper function. The components connecting to the RSN input should be placed in close proximity to that pin, so that no interference is injected into the RSN pin. Ground plane surrounding the RSN pin is advisable. Analog ground (AGND) should be connected to battery ground (BGND) on the PCB in one point. The capacitors for the battery should be connected with short wide leads of the same length.