PBL38630-2

PBL38630-2 ERICSSON | Alldatasheet

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Description

The PBL 386 30/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated circuit for use in Digital Loop Carrier, FITL and other telecommunications equipment. The PBL 386 30/2 has been optimized for low total line interface cost and a high degree of flexibility in different applications. The PBL 386 30/2 emulates resistive loop feed, programmable between 2x50 Ω and 2x900 Ω , with short loop current limiting adjustable to max 45 mA. In the current limited region the loop feed is nearly constant current with a slight slope corresponding to 2x30kΩ . A second lower battery voltage may be connected to the device to reduce short loop power dissipation. The SLIC automatically switches between the two battery supply voltages without need for external components or external control. The SLIC incorporates loop current and ring trip detection functions. The PBL 386 30/2 is compatible with loop start signaling. Two- to four-wire and four- to two-wire voice frequency (VF) signal conversion is accomplished by the SLIC in conjunction with either a conventional CODEC/filter or with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable two-wire impendance, complex or real, is set by a simple external network. Longitudinal voltages are suppressed by a feedback loop in the SLIC and the longitudinal balance specifications meet the DLC requirements. The PBL 386 30/2 package options are 24-pin SSOP, 24-pin SOIC and 28-pin PLCC. Figure 1. Block diagram.

• 24-pin SSOP package
• High and low battery supply with automatic switching
• 65 mW on-hook power dissipation in active state
• On-hook transmission
• Long loop battery feed tracks Vbat for maximum line voltage
• Only +5 V feed in addition to battery
• Selectable transmit gain (1x or 0.5x)
• No power-up sequence
• Programmable signal headroom
• 43V open loop voltage @ -48V battery feed
• Constant loop voltage for line leakage <5 mA (RLeak ~ >10 kΩ @ -48V)
• Full longitudinal current capability during on-hook state
• Analog over temperature protection permits transmission while the protection circuit is active
• Integrated Ring Relay Driver
• -40°C to +85°C ambient temperature range 24-pin SOIC, 24-pin SSOP, 28-pin PLCC RRL Y DET PSG REF LP PLD PLC VTX RSN PTG BGND AGND VBAT VBAT2 VCC HP RINGX TIPX DR DT Ring Relay Driver Input Decoder and Control Ring Trip Comparator Line Feed Controller and Longitudinal Signal Suppression Off-hook Detector VF Signal Transmission Two-wire Interface POV PBL 386 30/2 PBL PBL 386 30/2

Parameter Symbol Min Max Unit Temperature, Humidity Storage temperature range TStg -55 +150 °C Operating temperature range TAmb -40 +110 °C Operating junction temperature range, Note 1 TJ -40 +140 °C Power supply, -40 °C ≤ TAmb ≤ +85 °C VCC with respect to A/BGND V CC -0.4 6.5 V VBat2 with respect to A/BGND V Bat2 VBat 0.4 V VBat with respect to A/BGND, continuous V Bat -75 0.4 V VBat with respect to A/BGND, 10 ms V Bat -80 0.4 V Power dissipation Continuous power dissipation at TAmb ≤ +85 °CP D 1.5 W Ground Voltage between AGND and BGND V G -0.3 0.3 V Relay Driver Ring relay supply voltage BGND+14 V Ring trip comparator Input voltage V DT , VDR VBat AGND V Input current I DT , IDR -5 5 mA Digital inputs, outputs (C1, C2, DET) Input voltage V ID -0.4 V CC V Output voltage V OD -0.4 V CC V TIPX and RINGX terminals, -40°C < TAmb < +85°C, VBat = -50V Maximum supplied TIPX or RINGX current I TIPX, IRINGX -100 +100 mA TIPX or RINGX voltage, continuous (referenced to AGND), Note 2 V TA , VRA -80 2 V TIPX or RINGX, pulse < 10 ms, tRep > 10 s, Note 2 V TA , VRA VBat -10 5 V TIPX or RINGX, pulse < 1 µs, tRep > 10 s, Note 2 V TA , VRA VBat -25 10 V TIPX or RINGX, pulse < 250 ns, tRep > 10 s, Notes 2 & 3 V TA , VRA VBat -35 15 V Recommended Operating Condition Parameter Symbol Min Max Unit Ambient temperature T Amb -40 +85 °C VCC with respect to AGND V CC 4.75 5.25 V VBat with respect to AGND V Bat -58 -8 V AGND with respect to BGND V G -100 100 mV Notes 1. The circuit includes thermal protection. Operation at or above 140°C junction temperature may degrade device reliability. 2. With the diodes DVB and DVB2 included, see figure 11. 3. R F1 and RF2 ≥ 20 Ω is also required. Pulse is applied to TIP and RING outside RF1 and RF2.

Figure 5. Overload level, VTXO , four-wire

Four-wire to two-wire, g4-2 6 relative to 0 dBm, 1.0 kHz. EL=0 V 0.3 kHz < f < 3.4 kHz -0.2 0.1 dB f = 8 kHz, 12 kHz, -1.0 0 dB 16 kHz -2.0 0 dB Four-wire to four-wire, g 4-4 6 relative to 0 dBm, 1.0 kHz, EL=0 V 0.3 kHz < f < 3.4 kHz -0.2 0.1 dB Insertion loss Two-wire to four-wire, G2-4 6 0 dBm, 1.0 kHz, Note 5 VTXG 2-4 = 20 · Log ; ERX = 0 -0.2 0.2 dB VTR PTG = AGND -6.22 -6.02 -5.82 dB Four-wire to two-wire, G4-2 6 0 dBm, 1.0 kHz, Note 6 VTRG 4-2 = 20 · Log ; EL = 0 -0.2 0.2 dB ERX Gain tracking Two-wire to four-wire 6 Ref. -10 dBm, 1.0 kHz, Note 7 -40 dBm to +3 dBm -0.1 0.1 dB -55 dBm to -40 dBm -0.2 0.2 dB Four-wire to two-wire 6 Ref. -10 dBm , 1.0 kHz -40 dBm to +3 dBm -0.1 0.1 dB -55 dBm to -40 dBm -0.2 0.2 dB Noise Idle channel noise at two-wire C-message weighting 12 dBrnC (TIPX-RINGX) or four-wire (VTX) output Psophometrical weighting -78 dBmp Note 8 Harmonic distortion Two-wire to four-wire 6 0 dBm -67 -50 dB Four-wire to two-wire 0.3 kHz < f < 3.4 kHz -67 -50 dB Battery feed characteristics Loop current, I L , in the current 12 18mA ≤ IL ≤ 45 mA 0.92 I L IL 1.08 IL mA limited region, reference A, B & C Open circuit state loop current, ILOC R L = 0Ω -100 0 100 µA Ref Parameter fig Conditions Min Typ Max Unit Figure 6. Frequency response, insertion loss, gain tracking. 1 << RL, RL = 600 kΩ ω C R T = 120 kΩ , RRX = 60 kΩ PBL 386 30/2 TIPX RINGX RSN VTX R T R RX E RX R L VTR ILDC C E L VTX

Programmable threshold, ILTh ILTh = 500 0.85·ILTh ILTh 1.15·ILTh mA RLD R LD in kΩ , ILTh ≥ 7 mA Ring trip comparator Offset voltage, ∆VDTDR Source resistance, RS = 0 Ω -20 0 20 mV Input bias current, IB IB = (IDT + IDR )/2 -200 -20 200 nA Input common mode range, VDT , VDR VBat+1 -1 V Ring relay driver Saturation voltage, V OL IOL = 50 mA 0.2 0.5 V Off state leakage current, ILk VOH = 12 V 10 µA Digital inputs (C1, C2) Input low voltage, VIL 0 0.5 V Input high voltage, VIH 2.5 V CC V Input low current, IIL VIL = 0.5 -50 µA Input high current, IIH VIH = 2.5 V 50 µA Detector output (DET) Output low voltage I OL = 0.5 mA 0.7 V Internal pull-up resistor 15 k Ω Power dissipation (VBat = -48V,VBat2 = -32V) P1 Open circuit state, C1, C2 = 0, 0 10 15 mW Active state, C1, C2 = 0, 1 P2 Longitudinal current = 0 mA, I L=0 mA (on-hook) 65 85 mW P3 R L =300Ω (off-hook) 730 mW P4 R L =800Ω (off-hook) 360 mW Power supply currents (VBat = -48V) VCC current, ICC Open circuit state 1.2 2.0 mA VBat current, IBat -0.10 -0.05 mA VCC current, ICC Active state 2.8 4.0 mA VBat current, IBat On-hook, Long Current = 0 mA -1.5 -1.0 mA Power supply rejection ratios V CC to 2- or 4-wire port Active State 30 42 dB VBat to 2- or 4-wire port f= 1kHz, V n = 100mV 36 45 dB VBat2 to 2- or 4-wire port 40 60 dB Temperature guard Junction threshold temperature, TJG 145 °C Thermal resistance 28-pin PLCC, θJP28plcc 39 °C/W 24-pin SOIC, θJP24soic 43 °C/W 24-pin SSOP, θJP24ssop 55 °C/W Parameter fig Conditions Min Typ Max Unit Ref

1. The overload level can be adjusted with the ROV resistor for higher levels e.g. min 3.1 VPeak and is specified at the two-wire port with the signal source at the four-wire receive port. 2. The two-wire impedance is programmable by selection of external component values according to: Z TRX = ZT/|G2-4S α RSN | where: ZTRX = impedance between the TIPX and RINGX terminals ZT = programming network between the VTX and RSN terminals G 2-4S = transmit gain, nominally = 1 (or 0.5 see pin PTG) α RSN = receive current gain, nominally = 200 (current defined as positive flowing into the receivesumm- ing node, RSN, and when flowing from ring to tip). 3. Higher return loss values can be achieved by adding a reactive component to R T, the two-wire terminating impedance programming resistance, e.g. by dividing RT into two equal halves and connecting a capacitor from the common point to ground. 4. The overload level level can be adjusted with the R OV resistor for higher levels e.g. min 3.1 VPeak and is specified at the four-wire transmit port, VTX, with the signal source at the two-wire port. Note that the gain from the two-wire port to the four-wire transmit port is G 2-4S = 1 (or 0.5 see pin PTG) 5. Pin PTG = Open sets transmit gain to nom. 0.0dB Pin PTG = AGND sets transmit gain to nom. -6.02 dB Secondary protection resistors RF impact the insertion loss as explained in the text, section Transmission. The specified insertion loss is for R F = RP = 0. 6. The specified insertion loss tolerance does not include errors caused by external components. 7. The level is specified at the two-wire port. 8. The two-wire idle noise is specified with the port terminated in 600 Ω (RL) and with the four-wire receive port grounded (ERX = 0; see figure 6). The four-wire idle noise at VTX is specified with the two- wire port terminated in 600 Ω (RL). The noise specification is referenced to a 600 Ω programmed two-wire impedance level at VTX. The four-wire receive port is grounded (ERX = 0).

Figure 7. Pin configuration, 24-pin SSOP, 24-pin SOIC and 28 pin PLCC package, top view. 2 RRLY R ing R elay driver output. The relay coil may be connected to maximum +14V. 3 HP Connection for H igh Pass filter capacitor, CHP . Other end of CHP connects to TIPX. protection components and ring relay (and optional test relay). 6 BGND B attery G round, should be tied together with AGND. protection components and ring relay (and optional test relay). 8 VBAT Battery supply Voltage. Negative with respect to AGND. 9 VBAT2 An optional second (2) Battery Voltage connects to this pin. resistor connected from this pin to VBAT.

11 NC N o internal C onnection

12 LP Connection for Low Pass filter capacitor, CLP. Other end of CLP connects to VBAT. level low, indicating off-hook condition. The external ring trip network connects to this input. level low, indicating off-hook condition. The external ring trip network connects to this input.

Table 1. SLIC operating states. 15 NU Pin N ot U sed. Must be connected to AGND. 16 C2 C1 and C2 are digital inputs (internal pull-up) controlling the SLIC operating states. 17 C1 Refer to section "Operating states" for details. 18 DET Detector output. Active low when indicating loop detection and ring trip.

19 NC N o internal C onnection

connected from this pin to AGND. voltage can be set to higher values. 24 REF A Reference, 49.9 kΩ , resistor should be connected from this pin to AGND.

25 NC N o internal C onnection

connect to the receive summing node. A resistor should be connected from this pin to AGND. 27 AGND Analog Ground, should be tied together with BGND. reproduced as an unbalanced GND referenced signal at VTX with a gain of one (or one half, see pin PTG). The two-wire impedance programming network connects between VTX and RSN.

to four-wire gain (transmit direction). IL is the ac metallic current. impedance at voice frequencies. ZRX controls four- to two-wire gain. to metallic loop current gain = 200. in conventional CODEC/filter combinations. Figure 8. Simplified ac transmission circuit.

load of the VTX terminal is >20 kΩ . longitudinal currents in opposing phase. and ground, can be used for RFI filtering. to ground impedance of 1/(2⋅π⋅f⋅C RC ). Figure 9. Hybrid function. may occur at DTMF signalling. LP for different feeding characteristics. Table 1. RSG , CLP and CHP values for differ- ent feeding characteristics.

Figure 11. Single-channel subscriber line interface with PBL 386 30/2 and combination CODEC/filter. TX can not handle more than 3,2 VPeak. lated if the PTG is shorted.

1. Decide what overhead voltage(V
2. In figure 10 the corresponding ROV for

the decided VTRO can be found.

1. If the overhead voltage exceeds
2. RP1 and RP2 may be omitted if DVB is in place.

ringing source to tip and ring. Figure 12. Battery feed characteristics (without the protection resistors on the line).

Ordering Information

Package Temp. Range Part No. 24 pin SSOP Tape & Reel -40° - +85° C PBL 386 30/2SHT 24 pin SOIC Tube -40 ° - +85° C PBL 386 30/2SOS 24 pin SOIC Tape & Reel -40° - +85° C PBL 386 30/2SOT 28 pin PLCC Tube -40 ° - +85° C PBL 386 30/2QNS 28 pin PLCC Tape & Reel -40° - +85° C PBL 386 30/2QNT Information given in this data sheet is believed to be accurate and reliable. However no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Ericsson Microelectronics. These products are sold only according to Ericsson Microelectronics' general conditions of sale, unless otherwise confirmed in writing. Specifications subject to change without notice. 1522-PBL 386 30/2 Uen Rev. B © Ericsson Microelectronics AB 2000 Ericsson Microelectronics AB SE-164 81 Kista-Stockholm, Sweden Telephone: +46 8 757 50 00 This product is an original Ericsson product protected by US, European and other patents. may be applied to the SLIC. Secondary Protection The circuit shown in figure 11 utilizes series resistors together with a programmable overvoltage protector (e.g. Power Innovations TISPPBL2), serv- ing as a secondary protection. The TISPPBL2 is a dual forward-con- ducting buffered p-gate overvoltage pro- tector. The protector gate references the protection (clamping) voltage to negative supply voltage (i e the battery voltage, V B). As the protection voltage will track the negative supply voltage the overvoltage stress on the SLIC is minimized. Positive overvoltages are clamped to ground by a diode. Negative overvoltages are initially clamped close to the SLIC nega- tive supply rail voltage and the protector will crowbar into a low voltage on-state condi- tion, by firing an internal thyristor. A gate decoupling capacitor, C GG , is needed to carry enough charge to supply a high enough current to quickly turn on the thyristor in the protector. C GG shall be placed close to the overvoltage protection device. Without the capacitor even the low inductance in the track to the V Bat supply will limit the current and delay the activation of the thyristor clamp. The fuse resistors R F serve the dual purposes of being non- destructive energy dissipators, when transients are clamped and of being fuses, when the line is ex- posed to a power cross. If a PTC is chosen for R F, note that it is important to always use PTC´s in series with resistors not sensitive to temperature, as the PTC will act as a capacitance for fast transients and therefore will not protect the SLIC. Power-up Sequence No special power-up sequence is neces- sary except that ground has to be present before all other power supply voltages. Printed Circuit Board Layout Care in PCB layout is essential for proper function. The components connecting to the RSN input should be placed in close proximity to that pin, so that no interference is injected into the RSN pin. Ground plane surrounding the RSN pin is advisable. Analog ground (AGND) should be con- nected to battery ground (BGND) on the PCB in one point. The capacitors for the battery should be connected with short wide leads of the same length.