PBL38620-2 ERICSSON | Alldatasheet

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Description

The PBL 386 20/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated circuit for use in PBX,Terminal adapters and other telecommunications equipment. The PBL 386 20/2 has been optimized for low total line interface cost and a high degree of flexibility in different applications. The PBL 386 20/2 has constant current feed, programmable to max. 30 mA. A second lower battery voltage may be connected to the device to reduce short loop power dissipation. The SLIC automatically switches between the two battery supply voltages without need for external components or external control. The SLIC incorporates loop current, ground key and ring trip detection functions. The PBL 386 20/2 is compatible with loop start signaling. Two- to four-wire and four- to two-wire voice frequency (VF) signal conversion is accomplished by the SLIC in conjunction with either a conventional CODEC/filter or with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable two-wire impedance, complex or real, is set by a simple external network. Longitudinal voltages are suppressed by a feedback loop in the SLIC and the longitudinal balance specifications meet Bellcore TR909 requirements. The PBL 386 20/2 package options are 24-pin SSOP, 24-pin SOIC and 28 pin PLCC. Figure 1. Block diagram.

  • 24-pin SSOP package
  • High and low battery with automatic switching
  • 60 mW on-hook power dissipation in active state
  • On-hook transmission
  • Long loop battery feed tracks Vbat for maximum line voltage
  • Only +5 V feed in addition to battery
  • Selectable transmit gain (1x or 0.5x)
  • No power-up sequence
  • 44V open loop voltage @ -48V battery feed
  • Full longitudinal current capability during on-hook state
  • Analog over temperature protection permits transmission while the protection circuit is active
  • Integrated Ring Relay driver
  • Ground key detector
  • Programmable signal headroom24-pinSOIC, 24-pin SSOP, 28-pin PLCC RRLY DET PSG REF LP PLD PLC VTX RSN PTG BGND AGND VBAT VBAT2 VCC HP RINGX TIPX DR DT Ring Relay Driver Input Decoder and Control Ring Trip Comparator Ground Key Detector Line Feed Controller and Longitudinal Signal Suppression Off-hook Detector VF Signal Transmission Two-wire Interface POV PBL 386 20/2 PBL 386 20/2 PBL 386 20/2

Parameter Symbol Min Max Unit Temperature, Humidity Storage temperature range T Stg -55 +150 °C Operating temperature range T Amb -40 +110 °C Operating junction temperature range, Note 1 T J -40 +140 °C Power supply, 0°C ≤ TAmb ≤ +70°C VCC with respect to A/BGND V CC -0.4 6.5 V VBat2 with respect to A/BGND V Bat2 VBat 0.4 V VBat with respect to A/BGND, continuous V Bat -75 0.4 V VBat with respect to A/BGND, 10 ms V Bat -80 0.4 V Power dissipation Continuous power dissipation at TAmb ≤ +70 °CP D 1.5 W Ground Voltage between AGND and BGND V G -0.3 0.3 V Relay Driver Ring relay supply voltage BGND+14 V Ring trip comparator Input voltage V DT , VDR VBat AGND V Input current I DT , IDR -5 5 mA Digital inputs, outputs (C1, C2, C3, DET) Input voltage V ID -0.4 V CC V Output voltage V OD -0.4 V CC V TIPX and RINGX terminals, 0°C < TAmb < 70°C, VBat = -50V Maximum supplied TIPX or RINGX current I TIPX, IRINGX -100 +100 mA TIPX or RINGX voltage, continuous (referenced to AGND), Note 2 V TA , VRA -80 2 V TIPX or RINGX, pulse < 10 ms, tRep > 10 s, Note 2 V TA , VRA VBat -10 5 V TIPX or RINGX, pulse < 1 µs, tRep > 10 s, Note 2 V TA , VRA VBat -25 10 V TIPX or RINGX, pulse < 250 ns, tRep > 10 s, Notes 2 & 3 V TA , VRA VBat -35 15 V Recommended Operating Condition Parameter Symbol Min Max Unit Ambient temperature T Amb 0 +70 °C VCC with respect to AGND V CC 4.75 5.25 V VBat with respect to AGND V Bat -58 -8 V AGND with respect to BGND V G -100 100 mV Notes 1. The circuit includes thermal protection. Operation at or above 140°C junction temperature may degrade device reliability. 2. With the diodes DVB and DVB2 included, see figure 12. 3. RF1 and RF2 ≥ 20 Ω is also required. Pulse is applied to TIP and RING outside RF1 and RF2.

Four-wire to two-wire, g4-2 6 relative to 0 dBm, 1.0 kHz. EL=0 V 0.3 kHz < f < 3.4 kHz -0.2 0.1 dB f = 8 kHz, 12 kHz, -1.0 0 dB 16 kHz -2.0 0 dB Four-wire to four-wire, g 4-4 6 relative to 0 dBm.1.0 kHz, EL=0 V 0.3 kHz < f < 3.4 kHz -0.2 0.1 dB Insertion loss Two-wire to four-wire, G2-4 6 0 dBm, 1.0 kHz, Note 5 V TXG 2-4 = 20 · Log ; ERX = 0 -0.2 0.2 dB VTR PTG = AGND -6.22 -6.02 -5.82 dB Four-wire to two-wire, G4-2 6 0 dBm, 1.0 kHz, Note 6 V TRG 4-2 = 20 · Log ; EL = 0 -0.2 0.2 dB ERX Gain tracking Two-wire to four-wire 6 Ref. -10 dBm, 1.0 kHz, Note 7 -40 dBm to + 0 dBm -0.1 0.1 dB -55 dBm to -40 dBm -0.2 0.2 dB Four-wire to two-wire 6 Ref. -10 dBm -40 dBm to + 0 dBm -0.1 0.1 dB -55 dBm to -40 dBm -0.2 0.2 dB Noise Idle channel noise at two-wire C-message weighting 12 dBrnC (TIPX-RINGX) or four-wire (VTX) output Psophometrical weighting -78 dBmp Note 8 Harmonic distortion Two-wire to four-wire 6 0 dBm -67 -50 dB Four-wire to two-wire 0.3 kHz < f < 3.4 kHz -67 -50 dB Battery feed characteristics Constant loop current, I LProg 12 I LProg = 1 000 - 4.0 (mA) 0.92 I LProg ILProg 1.08 ILProg mA R LC ILProg @ 30 mA 12 I LProg = 1 000 - 4.2 (mA) 0.95 I LProg ILProg 1.05 ILProg mA R LC ILProg @ 18 mA 12 I LProg = 1 000 - 3.9 (mA) 0.94 I LProg ILProg 1.06 ILProg mA R LC R LC in kΩ Open circuit state loop current, I LOC R L = 0Ω -100 0 100 µA Ref Parameter fig Conditions Min Typ Max Unit Figure 6. Frequency response, insertion loss, gain tracking. 1 << RL, RL = 600 Ω ω C R T = 120 kΩ , RRX = 60 kΩ PBL 386 20/2 TIPX RINGX RSN VTX R T R RX E RX R L VTR ILDC C E L VTX

Programmable threshold, ILTh ILTh = 500 0.85·ILTh ILTh 1.15·ILTh mA RLD R LD in kΩ , ILTh ≥ 7 mA Ground key detector Ground key detector threshold TIPX and IRINGX difference to trigger ground key det.) 10 16 22 mA Ring trip comparator Offset voltage, ∆V DTDR Source resistance, RS = 0 Ω -20 0 20 mV Input bias current, IB IB = (IDT + IDR )/2 -200 -20 200 nA Input common mode range, VDT , VDR VBat+1 -1 V Ring relay driver Saturation voltage, V OL IOL = 50 mA 0.2 0.5 V Off state leakage current, ILk VOH = 12 V 10 µA Digital inputs (C1, C2, C3) Input low voltage, VIL 0 0.5 V Input high voltage, VIH 2.5 V CC V Input low current, IIL VIL = 0.5 -50 µA Input high current, IIH VIH = 2.5 V 50 µA Detector output (DET) Output low voltage I OL = 0.5 mA 0.7 V Internal pull-up resistor 15 k Ω Power dissipation (VBat = -48V, VBat2 = -17V) P1 Open circuit state, C1, C2, C3 = 0, 0, 0 10 15 mW Active state, C1, C2, C3 = 0, 1, 0 P2 Longitudinal current = 0 mA, I L=0 mA (on-hook) 60 80 mW P3 R L = 300 Ω (off-hook) 290 mW P4 R L = 500 Ω (off-hook) 145 mW Power supply currents (VBat = -48V) VCC current, ICC Open circuit state 1.2 2.0 mA VBat current, IBat -0.1 -0.05 mA VCC current, ICC Active state 2.8 4.0 mA VBat current, IBat On-hook, Long Current = 0 mA -1.5 -1.0 mA Power supply rejection ratios V CC to 2- or 4-wire port Active State 30 42 dB VBat to 2- or 4-wire port f = 1 kHz V n = 100mV 36 45 dB VBat2 to 2- or 4-wire port 40 60 dB Temperature guard Junction threshold temperature, TJG 145 °C Thermal resistance 28-pin PLCC, θJP28plcc 39 °C/W 24-pin SOIC, θJP24soic 43 °C/W 24-pin SSOP, θJP24ssop 55 °C/W Parameter fig Conditions Min Typ Max Unit Ref

  1. The overload level can be adjusted with the resistor ROV for higher levels e.g. min 3.1 VPeak and is specified at the two-wire port with the signal source at the four-wire receive port. 2. The two-wire impedance is programmable by selection of external component values according to: ZTRX = ZT/|G2-4S α RSN | where: ZTRX = impedance between the TIPX and RINGX terminals ZT = programming network between the VTX and RSN terminals G 2-4S = transmit gain, nominally = 1 (or 0.5 see pin PTG) α RSN = receive current gain, nominally = 200 (current defined as positive flowing into the receivesumm- ing node, RSN, and when flowing from ring to tip). 3. Higher return loss values can be achieved by adding a reactive component to RT, the two-wire terminating impedance programming resistance, e.g. by dividing RT into two equal halves and connecting a capacitor from the common point to ground. 4. The overload level can be adjusted with the resistor R OV for higher levels e.g. min 3.1 VPeak and is specified at the four-wire transmit port, VTX, with the signal source at the two-wire port. Note that the gain from the two-wire port to the four-wire transmit port is G2-4S = 1 (or 0.5 see pin PTG) 5. Pin PTG = Open sets transmit gain to nom. 0.0dB Pin PTG = AGND sets transmit gain to nom. -6.02 dB Secondary protection resistors R F and tertiary protection resistors RP impact the insertion loss as explained in the text, section Transmission. The specified insertion loss is for RF = RP = 0. 6. The specified insertion loss tolerance does not include errors caused by external components. 7. The level is specified at the two-wire port. 8. The two-wire idle noise is specified with the port terminated in 600 ohms (RL) and with the four-wire receive port grounded (ERX = 0; see figure 6). The four-wire idle noise at VTX is specified with the two- wire port terminated in 600 ohms (R L). The noise specification is referenced to a 600 ohm programmed two- wire impedance level at VTX. The four-wire receive port is grounded (E RX = 0).

Figure 8. Pin configuration, 24-pin SSOP, 24-pin SOIC and 28 pin PLCC package, top view. 2 RRLY R ing R elay driver output. The relay coil may be connected to maximum +14V. 3 HP Connection for H igh Pass filter capacitor, CHP . Other end of CHP connects to TIPX. 4N C N o internal C onnection. protection components and ring relay (and optional test relay). 6 BGND B attery G round, should be tied together with AGND. protection components and ring relay (and optional test relay). 8 VBAT Battery supply Voltage. Negative with respect to AGND. 9 VBAT2 An optional second (2) Battery Voltage connects to this pin. 11 NC N o internal C onnection. 12 LP Connection for Low Pass filter capacitor, CLP. Other end of CLP connects to VBAT. level low, indicating off-hook condition. The external ring trip network connects to this input.

0000 Open circuit -

1001 Ringing state Ring trip detector (active low)

2010 Active state Loop detector (active low)

3011 Not applicable -

4100 Not applicable -

5101 Active state Ground key detector (active high)

6110 Not applicable -

7111 Not applicable -

Table 1. SLIC operating states. level low, indicating off-hook condition. The external ring trip network connects to this input. 19 NC N o internal C onnection. connected from this pin to AGND. connected from this pin to AGND. 24 REF A Reference, 49.9 kΩ , resistor should be connected from this pin to AGND. 25 NC N o internal C onnection. receive gain connect to the receive summing node. A resistor should be connected from this pin to AGND. 27 AGND Analog Ground, should be tied together with BGND. reproduced as an unbalanced GND referenced signal at VTX with a gain of one (or one half, see pin PTG). The two-wire impedance programming network connects between VTX and RSN.

to four-wire gain (transmit direction). IL is the ac metallic current. R P is part of the SLIC protection. impedance at voice frequencies. ZRX controls four- to two-wire gain. to metallic loop current gain = 200. combinations. Please, refer to figure 10. load of the VTX terminal is >20 kΩ . Figure 9. Simplified ac transmission circuit.

may occur at DTMF signalling. Table 1. RSG , CLP and CHP values for cons- tant current feeding characteristics. Ericsson Microelectronics for assistance. “Programmable overhead voltage(POV)”. Table 2. Battery overhead. where RLC is in kΩ for ILProg in mA. to reduce short loop power dissipation. sheets for design information. longitudinal currents in opposing phase. and ground, can be used for RFI filtering. Figure 10. Hybrid function.

even if the first battery voltage disappears. VB2 , DBB and DVB2 are removed. RX , is dc biased with +1.25V. CODEC at the receive output. For the value on IRSN , see table 3. Table 3. The SLIC internal bias current with positive when floating into the terminal RSN. figure 11. The R TX can not handle more than 3.2 VPeak.

  1. In figure 11 the corresponding ROV

for the decided VTRO can be found.

  1. If the overhead voltage exceeds

3.2 VPeak , the G2-4S gain has to be

bit wide control interface C1, C2 and C3. description of the control interface. DET to a logical low level when selected. values, please refer to the datasheet. the ringing source to tip and ring.

that may be applied to the SLIC. ting buffered p-gate overvoltage protector. stress on the SLIC is minimized. condition, by firing an internal thyristor. close to the overvoltage protection device. Figure 12. single-channel subscriber line interface with PBL 386 20/2 and combination CODEC/filter. 1) RP1 and RP2 may be omitted if DVB is in place.

Ordering Information

Package Temp. Range Part No. 24 pin SSOP Tape & Reel 0° - +70° C PBL 386 20/2SHT 24 pin SOIC Tube 0 ° - +70° C PBL 386 20/2SOS 24 pin SOIC Tape & Reel 0° - +70° C PBL 386 20/2SOT 28 pin PLCC Tube 0 ° - +70° C PBL 386 20/2QNS 28 pin PLCC Tape & Reel 0° - +70° C PBL 386 20/2QNT Specifications subject to change without notice. 1522-PBL 386 20/2 Uen Rev. A © Ericsson Microelectronics AB 1999 Ericsson Microelectronics AB SE-164 81 Kista-Stockholm, Sweden Telephone: +46 8 757 50 00 Information given in this data sheet is believed to be accurate and reliable. However no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Ericsson Microelectronics AB. These products are sold only according to Ericsson Microelectronics AB' general conditions of sale, unless otherwise confirmed in writing. This product is an original Ericsson product protected by US, European and other patents. Power-up Sequence No special power-up sequence is necessary except that ground has to be present before all other power supply voltages. Printed Circuit Board Layout Care in PCB layout is essential for proper function. The components connecting to the RSN input should be placed in close proximity to that pin, such that no interference is injected into the RSN pin. Ground plane surrounding the RSN pin is advisable. Analog ground (AGND) should be connected to battery ground (BGND) on the PCB in one point.The capacitors for the battery should be connected with short wide leads of the same length.