PA502FMG

PA502FMG UNIKC | Alldatasheet

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P-Channel Logic Level Enhancement Mode MOSFET PRODUCT SUMMARY V(BR)DSS SOT-23 ABSOLUTE MAXIMUM RATINGS (TA = 25 ° C Unless Otherwise Noted) THERMAL RESISTANCE RATINGS UNITS ° C / W 1Pulse width limited by maximum junction temperature. MAXIMUMTHERMAL RESISTANCE Operating Junction & Storage Temperature Range SYMBOL PD Tj, Tstg 0.7 1.2 -55 to 150 °C ID -20V TA = 25 ° C TA = 70 ° C Power Dissipation Continuous Drain Current TA = 25 ° C Avalanche Current SYMBOL VDS Pulsed Drain Current1 RDS(ON) TA = 70 ° C PARAMETERS/TEST CONDITIONS Drain-Source Voltage Gate-Source Voltage 150mΩ @VGS = -4.5V -3A RqJA 110Junction-to-Ambient VGS LIMITS ID IDM TYPICAL W UNITS -12 -1.9 ± 12 V-20 IAS -12 A Avalanche Energy L = 0.1 mH EAS 7 mJ REV 1.0 1 2014/8/25

P-Channel Logic Level Enhancement Mode MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25 ° C, Unless Otherwise Noted) MIN TYP MAX -20 -0.5 -0.9 -1.2 ± 100 nA -10 -6 A 118 250 87 150 16 S 415 119 6.3 Ω 5.8 2.4 3 A -1.2 V 21 nS 7 nC 1Pulse test : Pulse Width  300 msec, Duty Cycle  2％. 2Independent of operating temperature. IF = -1A, VGS = 0V Continuous Current Forward Voltage1 IS VSD nC nS SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICE ( TJ = 25 °C ) Fall Time2 Qg Qgs Qgd td(on) tr Total Gate Charge2 VGS = -4.5V, ID = -3A td(off) tf Gate-Drain Charge2 Turn-On Delay Time2 Rise Time2 Turn-Off Delay Time2 VDD = -10V ID @ -3A, VGS = -4.5V, RG = 6Ω Gate-Source Charge2 VDS = 0.5V(BR)DSS, VGS = -4.5V, ID = -3A Input Capacitance Output Capacitance Reverse Transfer Capacitance Crss Gate Resistance Rg VGS = 0V, VDS = 0V, f = 1MHz VGS = 0V, VDS = -10V, f = 1MHz ID(ON) gfs VDS = -5V, VGS = -4.5V UNITSPARAMETER SYMBOL TEST CONDITIONS VGS = -2.5V, ID = -1A VDS = -5V, ID = -3A RDS(ON) Forward Transconductance1 VGS = 0V, ID = -250mAV(BR)DSS Zero Gate Voltage Drain Current Gate-Body Leakage VDS = -16V, VGS = 0V On-State Drain Current1 Gate Threshold Voltage DYNAMIC V IGSS IDSS mA Drain-Source Breakdown Voltage VDS = -16V, VGS = 0V , TJ = 55 ° C VDS = VGS, ID = -250mAVGS(th) VDS = 0V, VGS = ± 12V STATIC LIMITS Drain-Source On-State Resistance1 mΩ Reverse Recovery Time Reverse Recovery Charge trr Qrr IF = -1A,dIF/dt = 100 A/ms pF Ciss Coss REV 1.0 2 2014/8/25

P-Channel Logic Level Enhancement Mode MOSFET REV 1.0 3 2014/8/25

P-Channel Logic Level Enhancement Mode MOSFET REV 1.0 4 2014/8/25

P-Channel Logic Level Enhancement Mode MOSFET REV 1.0 5 2014/8/25