PA102FMA UNIKC | Alldatasheet

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P-Channel Logic Level Enhancement Mode MOSFET PRODUCT SUMMARY V(BR)DSS SOT-23(S) ABSOLUTE MAXIMUM RATINGS (TA = 25 ° C Unless Otherwise Noted) THERMAL RESISTANCE RATINGS UNITS ° C / W 1Pulse width limited by maximum junction temperature. 2The value of RθJA is measured with the device mounted on 1in2 FR-4 board with 2oz. Copper, in a still air environment with TA =25° C. W0.6 RqJA PD TA = 70 ° CPower Dissipation TJ, Tstg ID TA = 25 ° C -20V Continuous Drain Current TA= 70 ° C PARAMETERS/TEST CONDITIONS RDS(ON) Drain-Source Voltage 118mΩ @VGS = 4.5V -2A Junction-to-Ambient2 THERMAL RESISTANCE LIMITS TA = 25 ° C MAXIMUM Gate-Source Voltage ± 12 UNITS -1.7 TYPICAL VDS -20 V ID IDM SYMBOL Operating Junction & Storage Temperature Range SYMBOL °C-55 to 150 130 A V 0.9 VGS Pulsed Drain Current1 REV 1.0 1 2014-2-26

P-Channel Logic Level Enhancement Mode MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25 ° C, Unless Otherwise Noted) MIN TYP MAX -20 -0.3 -0.75 -1.2 ± 100 nA -10 124 215 87 118 68 85 7.5 S 364 0.7 2.1 0.75 A 1.2 V 11 nS 2.2 nC 1Pulse test : Pulse Width  300 msec, Duty Cycle  2%. 2Independent of operating temperature. LIMITSPARAMETER Output Capacitance VGS = -10V , ID = -2A VDS = -16V, VGS = 0V, TJ = 125 ° C SYMBOL Gate-Drain Charge2 Gate-Source Charge2 Reverse Transfer Capacitance Total Gate Charge2 Input Capacitance VGS = 0V, VDS = -10V, f = 1MHz Rise Time2 Turn-Off Delay Time2 Fall Time2 Gate Threshold Voltage Drain-Source On-State Resistance1 Qg Zero Gate Voltage Drain Current IGSS IF = -2A, VGS = 0V nSVDD = -10V, ID @ -1A, VGS = -4.5V, RG= 6Ω SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TJ = 25 ° C) td(on) tr td(off) tf Turn-On Delay Time2 QrrReverse Recovery Charge Continuous Current Forward Voltage1 Reverse Recovery Time IS VSD trr nCQgs mA DYNAMIC mΩ VDS = -16V, VGS = 0V Qgd pF IDSS VDS = -10V , VGS = -4.5V, ID = -2A Ciss VDS = -5V, ID = -2A VDS = 0V, VGS = ± 12V gfs RDS(ON) Forward Transconductance1 VGS = -4.5V, ID = -2A Gate-Body Leakage V(BR)DSS TEST CONDITIONS STATIC VGS = 0V, ID = -250mA VGS = 0V, dlS/dt = 100A / μS UNITS Coss Crss VGS = -2.5V, ID = -1A Drain-Source Breakdown Voltage V VDS = VGS, ID = -250mAVGS(th) REV 1.0 2 2014-2-26

P-Channel Logic Level Enhancement Mode MOSFET REV 1.0 3 2014-2-26

P-Channel Logic Level Enhancement Mode MOSFET REV 1.0 4 2014-2-26

P-Channel Logic Level Enhancement Mode MOSFET REV 1.0 5 2014-2-26