PA002FMG UNIKC | Alldatasheet

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P-Channel Logic Level Enhancement Mode MOSFET PRODUCT SUMMARY V(BR)DSS SOT-23 ABSOLUTE MAXIMUM RATINGS (TA = 25 ° C Unless Otherwise Noted) THERMAL RESISTANCE RATINGS UNITS ° C / W 1Pulse width limited by maximum junction temperature. MAXIMUMTHERMAL RESISTANCE Operating Junction & Storage Temperature Range SYMBOL PD Tj, Tstg 0.64 -55 to 150 °C ID -20V TA = 25 ° C TA = 70 ° C Power Dissipation Continuous Drain Current TA = 25 ° C SYMBOL VDS Pulsed Drain Current1 RDS(ON) TA = 70 ° C PARAMETERS/TEST CONDITIONS Drain-Source Voltage Gate-Source Voltage 100mΩ @VGS = -4.5V -3A RqJA 125Junction-to-Ambient VGS LIMITS ID IDM TYPICAL W UNITS -10 -2.4 ± 12 V A -20 REV 1.1 1 2014-3-10

P-Channel Logic Level Enhancement Mode MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25 ° C, Unless Otherwise Noted) MIN TYP MAX -20 -0.3 -0.8 -1.2 ± 100 nA -10 -10 A 185 240 116 140 84 100 7 S 540 4.5 Ω 6.2 0.6 1.6 -1.6 A -1.2 V 1Pulse test : Pulse Width  300 msec, Duty Cycle  2％. 2Independent of operating temperature. IF = -3A, VGS = 0V Continuous Current Forward Voltage1 IS VSD nC nS SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICE ( TC = 25 °C ) Fall Time2 Qg Qgs Qgd td(on) tr Drain-Source On-State Resistance1 VGS = -4.5V, ID = -3A mΩ td(off) tf Gate-Drain Charge2 Turn-On Delay Time2 Rise Time2 Turn-Off Delay Time2 VDD = -10V ID @ -1A, VGS = -4.5V, RG = 6Ω Total Gate Charge2 Gate-Source Charge2 VDS = 0.5V(BR)DSS, VGS = -4.5V, ID = -3A Input Capacitance Output Capacitance Reverse Transfer Capacitance Crss Gate Resistance Rg VGS = 15mV, VDS = 0V, f = 1MHz UNITPARAMETER SYMBOL TEST CONDITIONS Forward Transconductance1 VGS = 0V, ID = -250mAV(BR)DSS Zero Gate Voltage Drain Current Gate-Body Leakage VDS = -16V, VGS = 0V On-State Drain Current1 ID(ON) gfs VDS = -5V, VGS = -4.5V VGS = 0V, VDS = -10V, f = 1MHz pF Ciss Coss VGS(th) VGS = -2.5V, ID = -2.5A VDS = -5V, ID = -3A RDS(ON) Gate Threshold Voltage DYNAMIC V IGSS IDSS mA Drain-Source Breakdown Voltage VGS = -1.8V, ID = -1A VDS = -16V, VGS = 0V , TJ = 125 ° C VDS = VGS, ID = -250mA VDS = 0V, VGS = ± 12V STATIC LIMITS REV 1.1 2 2014-3-10

P-Channel Logic Level Enhancement Mode MOSFET REV 1.1 3 2014-3-10

P-Channel Logic Level Enhancement Mode MOSFET REV 1.1 4 2014-3-10

P-Channel Logic Level Enhancement Mode MOSFET REV 1.1 5 2014-3-10

P-Channel Logic Level Enhancement Mode MOSFET REV 1.1 6 2014-3-10