P2206BV UNIKC | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 8
Technical content
N-Channel Logic Level Enhancement Mode MOSFET PRODUCT SUMMARY V(BR)DSS SOP-8 ABSOLUTE MAXIMUM RATINGS (TA = 25 ° C Unless Otherwise Noted) THERMAL RESISTANCE RATINGS UNITS ° C / W 1Pulse width limited by maximum junction temperature. 2The value of RqJA is measured with the device mounted on 1in2 FR-4 board with 2oz. Copper, in a still air environment with TA =25° C. Junction-to-Ambient2 Tj, Tstg SYMBOL ID PD RqJA Pulsed Drain Current1 Avalanche Current Power Dissipation EAS THERMAL RESISTANCE Avalanche Energy TYPICAL TA =70 ° C Junction & Storage Temperature Range L = 0.1mH ID TA = 25 ° C 60V Continuous Drain Current TA = 70 ° C PARAMETERS/TEST CONDITIONS RDS(ON) 22.5mΩ @VGS = 10V 7A Gate-Source Voltage Drain-Source Voltage TA= 25 ° C V W UNITS 5.3 33 mJ 1.3 IDM SYMBOL LIMITS A VVGS VDS ± 20 IAS °C-55 to 150 MAXIMUM REV 1.0 1 2018/7/31
N-Channel Logic Level Enhancement Mode MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25 ° C, Unless Otherwise Noted) MIN TYP MAX 1.3 1.8 2.3 ± 100 nA 20 30 17.5 22.5 14 S 1005 125 0.9 Ω 3.2 8.6 1.5 A 1.3 V 18 nS 7 nC 1Pulse test : Pulse Width 300 msec, Duty Cycle 2%. 2Independent of operating temperature. Drain-Source On-State Resistance1 RDS(ON) Zero Gate Voltage Drain Current IGSSGate-Body Leakage VGS(th) V mΩ VGS = 4.5V, ID = 7A SYMBOL UNITS VGS = 10V, ID = 7A Gate-Drain Charge2 VDS = 40V, VGS = 0V, TJ = 55 ° C PARAMETER Drain-Source Breakdown Voltage Input Capacitance Qgd Output Capacitance Qg(VGS=10V) Forward Transconductance1 Gate Resistance Gate-Source Charge2 Total Gate Charge2 VGS = 0V, VDS = 0V, f = 1MHz td(off) tf Turn-On Delay Time2 Rise Time2 Turn-Off Delay Time2 Fall Time2 V(BR)DSS TEST CONDITIONS IF = 7A, VGS = 0V nSVDD = 30V, ID @ 7A, VGS = 10V, RGEN = 6Ω SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TJ = 25 ° C) td(on) tr Diode Reverse Recovery Charge Continuous Current Forward Voltage1 Diode Reverse Recovery Time IS VSD trr Gate Threshold Voltage VDS = VGS, ID = 250mA LIMITS VGS = 0V, ID = 250mA VGS = 0V, VDS = 25V, f = 1MHz VDS = 48V, VGS = 0V gfs Ciss VDS = 5V, ID = 7A Reverse Transfer Capacitance nC Qgs mA pF STATIC DYNAMIC IF = 7A, dl/dt = 100A /mS VDS = 0V, VGS = ± 20V IDSS Coss Crss Rg VDS = 30V , ID = 7A Qrr Qg(VGS=4.5V) REV 1.0 2 2018/7/31
N-Channel Logic Level Enhancement Mode MOSFET REV 1.0 3 2018/7/31
N-Channel Logic Level Enhancement Mode MOSFET REV 1.0 4 2018/7/31
N-Channel Logic Level Enhancement Mode MOSFET REV 1.0 5 2018/7/31
N-Channel Logic Level Enhancement Mode MOSFET A. Marking Information B. Tape&Reel Information:2500pcs/Reel REV 1.0 6 2018/7/31
N-Channel Logic Level Enhancement Mode MOSFET REV 1.0 7 2018/7/31
N-Channel Logic Level Enhancement Mode MOSFET D.Label rule 标签内容(Label content) REV 1.0 8 2018/7/31