P1203EV

P1203EV UNIKC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 5

Technical content

P-Channel Logic Level Enhancement Mode MOSFET PRODUCT SUMMARY V(BR)DSS SOP- 08 ABSOLUTE MAXIMUM RATINGS (TA = 25 ° C Unless Otherwise Noted) THERMAL RESISTANCE RATINGS UNITS ° C / W 1Pulse width limited by maximum junction temperature. 2 The value of RqJA is measured with the device mounted on 1in2 FR-4 board with 2oz. Copper, in a still air environment with TA =25° C -46 105 mJ A Avalanche Current L = 0.1mHAvalanche Energy EAS IAS UNITS -90 -8.3 ± 25 V °C-55 to 150 MAXIMUM ID RDS(ON) TA = 70 ° C PARAMETERS/TEST CONDITIONS Drain-Source Voltage Gate-Source Voltage 12mΩ @VGS = -10V -10A ID -30V Continuous Drain Current LIMITS Pulsed Drain Current1 IDM VGS -10TA = 25 ° C -30 SYMBOL VDS Junction-to-Ambient2 RqJA 1.3 THERMAL RESISTANCE SYMBOL Power Dissipation TA = 70 ° C PD TJ, TSTG TA = 25 ° C Operating Junction & Storage Temperature Range TYPICAL REV 1.0 1 2014/9/16

P-Channel Logic Level Enhancement Mode MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25 ° C, Unless Otherwise Noted) MIN TYP MAX -30 -1 -1.7 -3 ± 100 nA -10 14 21 9 12 7.5 10 36 S 2980 394 391 2.1 Ω 200 100 -10 A -1.2 V 22 nS 9 nC 1Pulse test : Pulse Width  300 msec, Duty Cycle  2％. 2Independent of operating temperature. Drain-Source On-State Resistance1 RDS(ON) VGS = -20V, ID = -10A mΩ Gate Resistance Rg VGS = 0V, VDS = 0V, f = 1MHz VDS = 0V, VGS = ± 25V mA STATIC LIMITS UNITS Gate Threshold Voltage V IGSS pF VDS = -24V, VGS = 0VIDSS VDS = -20V, VGS = 0V , TJ = 55 ° C Reverse Transfer Capacitance VGS = 0V, VDS = -15V, f = 1MHz gfs DYNAMIC Coss Crss Qgd Qgs nCGate-Source Charge2 Gate-Drain Charge2 Turn-On Delay Time2 Rise Time2 Turn-Off Delay Time2 SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TJ = 25 ° C) IF = -10A, VGS = 0V nSVDS = -15V, ID@ -1A, VGS = -10V, RGS = 6Ω td(on) tr Output Capacitance Drain-Source Breakdown Voltage VGS = -4.5V, ID = -9A VDS = -10V, ID = -10A VGS(th) VGS = 0V, ID = -250mAV(BR)DSS Zero Gate Voltage Drain Current Qg VDS = 0.5V(BR)DSS, VGS = -10V, ID = -10A Ciss VGS = -10V, ID = -10A Total Gate Charge2 PARAMETER SYMBOL Input Capacitance Gate-Body Leakage Forward Transconductance1 VDS = VGS, ID = -250mA QrrReverse Recovery Charge TEST CONDITIONS Continuous Current trr td(off) tfFall Time2 IF = -10A, dlF/dt = 100A / mS Forward Voltage1 Reverse Recovery Time IS VSD REV 1.0 2 2014/9/16

P-Channel Logic Level Enhancement Mode MOSFET REV 1.0 3 2014/9/16

P-Channel Logic Level Enhancement Mode MOSFET REV 1.0 4 2014/9/16

P-Channel Logic Level Enhancement Mode MOSFET REV 1.0 5 2014/9/16