P1203EEA UNIKC | Alldatasheet

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P-Channel Logic Level Enhancement Mode MOSFET PRODUCT SUMMARY V(BR)DSS PDFN 3x3P ABSOLUTE MAXIMUM RATINGS (TA = 25 ° C Unless Otherwise Noted) TJ, TSTG TC = 25 ° C TC = 100 ° C EASAvalanche Energy L = 0.1mH RDS(ON) TC = 100 ° C PARAMETERS/TEST CONDITIONS Drain-Source Voltage Gate-Source Voltage 12mΩ @VGS = -10V -40A ID -30V SYMBOL VDS Pulsed Drain Current1 101 ± 25 ID TC = 25 ° C IDM Avalanche Current IAS Operating Junction & Storage Temperature Range -11 -40 2.2 1.4 -30 VGS LIMITS °C-55 to 150 mJ UNITS -95 V A W Continuous Drain Current2 Power Dissipation TA = 25 ° C TA = 70 ° C TA = 25 ° C TA = 70 ° C -25 PD REV1.2 1 2015/8/14

P-Channel Logic Level Enhancement Mode MOSFET THERMAL RESISTANCE RATINGS UNITS 1Pulse width limited by maximum junction temperature. 2Package limitation current is -30A. 3The value of RqJA is measured with the device mounted on 1 in2 FR-4 board with 2oz. Copper, in a still air environment with TA = 25° C. The value in any given application depends on the user's specific board design. ELECTRICAL CHARACTERISTICS (TJ = 25 ° C, Unless Otherwise Noted) MIN TYP MAX -30 -1 -1.5 -2.5 ± 100 nA -10 -95 A 13 19 8.8 12 31 S 2760 437 395 2.5 Ω 100 SYMBOL TEST CONDITIONS Drain-Source On-State Resistance1 RDS(ON) VGS = -10V, ID = -12A On-State Drain Current1 ID(ON) VDS = -5V, VGS = -10V Gate Threshold Voltage IDSS nSVDS = -15V, ID @ -12A, VGS = -10V, RGS = 6Ω Rise Time2 Turn-Off Delay Time2 td(on) tr td(off) tfFall Time2 Turn-On Delay Time2 THERMAL RESISTANCE SYMBOL TYPICAL VGS = 0V, ID = -250mAV(BR)DSS mA mΩ DYNAMIC VDS = 0V, VGS = ± 25V VDS = -24V, VGS = 0V nC VGS = 0V, VDS = -15V, f = 1MHz pF Ciss Coss Input Capacitance Output Capacitance Forward Transconductance1 Reverse Transfer Capacitance Crss VDS = -20V, VGS = 0V , TJ = 125 ° C VGS = -4.5V, ID = -9A VDS = -5V, ID = -12A Zero Gate Voltage Drain Current gfs STATIC LIMITS UNITSPARAMETER V IGSS Drain-Source Breakdown Voltage VGS(th) Gate-Body Leakage VDS = VGS, ID = -250mA MAXIMUM 4Steady-State RqJA ° C / WJunction-to-Ambient Junction-to-Ambient3 Steady-State 55 RqJC Qg(VGS=-10V) VDS = -15V, ID = -12A Total Gate Charge2 Qg(VGS=-4.5V) Gate-Drain Charge2 Gate-Source Charge2 Qgd Qgs Gate Resistance Rg VGS = 0V, VDS = 0V, f = 1MHz REV1.2 2 2015/8/14

P-Channel Logic Level Enhancement Mode MOSFET -40 A -1.2 V 21 nS 7 nC 1Pulse test : Pulse Width  300 msec, Duty Cycle  2％. 2Independent of operating temperature. 3Package limitation current is -30A. IF = -12A, dlF/dt = 100A / mS Reverse Recovery Charge trr Continuous Current3 IS Qrr Forward Voltage1 VSD IF = -12A, VGS = 0V SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TJ = 25 ° C) Reverse Recovery Time REV1.2 3 2015/8/14

P-Channel Logic Level Enhancement Mode MOSFET REV1.2 4 2015/8/14

P-Channel Logic Level Enhancement Mode MOSFET REV1.2 5 2015/8/14

P-Channel Logic Level Enhancement Mode MOSFET REV1.2 6 2015/8/14

P-Channel Logic Level Enhancement Mode MOSFET A. Marking Information(此产品代码为：B2） B. Tape&Reel Information:5000pcs/Reel REV1.2 7 2015/8/14

P-Channel Logic Level Enhancement Mode MOSFET REV1.2 8 2015/8/14

P-Channel Logic Level Enhancement Mode MOSFET D.Label rule 标签内容(Label content) REV1.2 9 2015/8/14