P1003EK

P1003EK UNIKC | Alldatasheet

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P-Channel Logic Level Enhancement Mode MOSFET PRODUCT SUMMARY V(BR)DSS ABSOLUTE MAXIMUM RATINGS (TA = 25 ° C Unless Otherwise Noted) Continuous Drain Current TC = 25 ° C(Package Limited) TC = 25 ° C (Silicon Limited) TC = 100 ° C Continuous Drain Current TA = 25 ° C TA = 70 ° C W 1.6 Power Dissipation EAS PD 2.5 Avalanche Energy L = 0.1mH TC = 25 ° C TC = 100 ° C TA = 25 ° C PDFN 5*6P VVGS -63 -40 ID -12 -10 Drain-Source Voltage VDS -30 Pulsed Drain Current1 TA = 70 ° C Avalanche Current RDS(ON) PARAMETERS/TEST CONDITIONS Gate-Source Voltage 10.5mΩ @VGS = -10V -30A ID -30V mJ UNITS -120 ID IDM SYMBOL -30 LIMITS A ± 25 IAS -45 Operating Junction & Storage Temperature Range -55 to 150 62.5 102 TJ, TSTG REV 1.0 1 2014/9/22

P-Channel Logic Level Enhancement Mode MOSFET THERMAL RESISTANCE RATINGS UNIT S 1Pulse width limited by maximum junction temperature. ELECTRICAL CHARACTERISTICS (TJ = 25 ° C, Unless Otherwise Noted) MIN TYP MAX -30 -1 -1.7 -3 ± 250 nA -120 A 13 16 8 10.5 10 S 2640 566 467 2.9 Ω mA VGS = 0V, VDS = -15V, f = 1MHz VGS = -10V, ID = -13A VDS = VGS, ID = -250mA PARAMETER Drain-Source On-State Resistance1 RDS(ON) VDS = 0V, VGS = ± 25VGate-Body Leakage IDSS THERMAL RESISTANCE SYMBOL TYPICA L RqJC TEST CONDITIONSSYMBOL Junction-to-Case Junction-to-Ambient MAXIMUM Qg(VGS =-4.5V) Output Capacitance Gate-Drain Charge2 Gate-Source Charge2 Reverse Transfer Capacitance Total Gate Charge2 Gate Resistance Qg(VGS =-10V) gfs nSVDS = -20V, ID @ -13A, VGS = -10V, RGS = 6ΩTurn-Off Delay Time2 Fall Time2 td(off) tf Turn-On Delay Time2 Rise Time2 td(on) tr nC Drain-Source Breakdown Voltage VGS = -4.5V, ID = -10A VDS = -5V, ID = -13A VGS(th) Forward Transconductance1 VGS = 0V, ID = -250mAV(BR)DSS Zero Gate Voltage Drain Current V VDS = 0.5V(BR)DSS,VGS = -10V, ID = -13A Ciss Coss Crss Qgd Qgs Rg VGS = 0V, VDS = 0V, f = 1MHz pF STATIC LIMITS UNIT S DYNAMIC mΩ VDS = -24V, VGS = 0V Input Capacitance Gate Threshold Voltage On-State Drain Current1 ID(ON) VDS = -5V, VGS = -10V IGSS VDS = -20V, VGS = 0V , TJ = 125 ° C ° C / WRqJA REV 1.0 2 2014/9/22

P-Channel Logic Level Enhancement Mode MOSFET -1 V 32.5 nS 17 nC 1Pulse test : Pulse Width  300 msec, Duty Cycle  2％. 2Independent of operating temperature. Forward Voltage1 VSD IF = -13A, VGS = 0V Reverse Recovery Time trr IF = -13A, dlF/dt = 100A / μS Reverse Recovery Charge Qrr SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TJ = 25 ° C) REV 1.0 3 2014/9/22

P-Channel Logic Level Enhancement Mode MOSFET REV 1.0 4 2014/9/22

P-Channel Logic Level Enhancement Mode MOSFET REV 1.0 5 2014/9/22

P-Channel Logic Level Enhancement Mode MOSFET REV 1.0 6 2014/9/22