P0AP03LCG UNIKC | Alldatasheet

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P-Channel Logic Level Enhancement Mode MOSFET PRODUCT SUMMARY V(BR)DSS SOT-89 ABSOLUTE MAXIMUM RATINGS (TA = 25 ° C Unless Otherwise Noted) THERMAL RESISTANCE RATINGS UNITS 1Pulse width limited by maximum junction temperature.

2 The value of RqJA

is measured with the device mounted on 1in2 FR-4 board with 2oz. Copper, in a still air environment with TA =25° C.The value in any given application depends on the user's specific board design. THERMAL RESISTANCE SYMBOL PD TJ, TSTG TA = 25 ° C Junction-to-Ambient2 RqJA Operating Junction & Storage Temperature Range TYPICAL 1.3 MAXIMUM Power Dissipation TA = 70 ° C SYMBOL LIMITS IAS Pulsed Drain Current1 -19Avalanche Current EAS Drain-Source Voltage VDS RDS(ON) TA = 70 ° C PARAMETERS/TEST CONDITIONS Gate-Source Voltage 28mΩ @VGS = -10V -6.5A ID -30V ID IDM Junction-to-Case Continuous Drain Current Avalanche Energy VGS -6.5TA = 25 ° C L = 0.1mH A RqJC UNITS -20 -5.2 ± 20 °C-55 to 150 mJ W -30 V 18 ° C / W61 REV 1.0 1 2017/2/20

P-Channel Logic Level Enhancement Mode MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25 ° C, Unless Otherwise Noted) MIN TYP MAX -30 -0.8 -1.7 -2.5 ± 100 nA -10 29 45 19 28 16 S 955 142 121 12 Ω 21.5 2.2 -2 A -1 V 12 nS 5 nC 1Pulse test : Pulse Width  300 msec, Duty Cycle  2％. 2Independent of operating temperature. Gate Resistance Rg VGS = 0V, VDS = 0V, f = 1MHz Reverse Recovery Time IF = -3.5A, dlF/dt = 100A / mS VSD Fall Time2 Forward Voltage1 TEST CONDITIONS mΩDrain-Source On-State Resistance1 RDS(ON) VGS = -10V, ID = -3.5A VDS = -20V, VGS = 0V , TJ = 125 ° C nSVDS = -15V, ID @ -3.5A, VGS = -10V, RGS = 6Ω td(on) tr td(off) tf Output Capacitance Gate-Drain Charge2 Gate-Source Charge2 QrrReverse Recovery Charge Continuous Current Turn-On Delay Time2 Rise Time2 Turn-Off Delay Time2 SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TJ = 25 ° C) IF = -3.5A, VGS = 0V IS VGS = 0V, VDS = -15V, f = 1MHz Reverse Transfer Capacitance trr Drain-Source Breakdown Voltage VGS = -4.5V, ID = -3A VDS = -10V, ID = -3.5A VGS(th) Forward Transconductance1 VGS = 0V, ID = -250mAV(BR)DSS Ciss Coss Crss Qgd Qgs gfs Gate Threshold Voltage DYNAMIC V IGSS pF VDS = -24V, VGS = 0V Gate-Body Leakage Input Capacitance IDSS VDS = VGS, ID = -250mA VDS = 0V, VGS = ± 20V Zero Gate Voltage Drain Current STATIC LIMITS UNITS Total Gate Charge2 VDS = -15V, VGS = -10V, ID = -3.5A nC Qg mA PARAMETER SYMBOL REV 1.0 2 2017/2/20

P-Channel Logic Level Enhancement Mode MOSFET REV 1.0 3 2017/2/20

P-Channel Logic Level Enhancement Mode MOSFET REV 1.0 4 2017/2/20

P-Channel Logic Level Enhancement Mode MOSFET REV 1.0 5 2017/2/20

P-Channel Logic Level Enhancement Mode MOSFET A. Marking Information B. Tape&Reel Information:1000pcs/Reel REV 1.0 6 2017/2/20

P-Channel Logic Level Enhancement Mode MOSFET REV 1.0 7 2017/2/20

P-Channel Logic Level Enhancement Mode MOSFET D.Label rule 标签内容(Label content) REV 1.0 8 2017/2/20