LP1030D SUTEX | Alldatasheet

Document overview

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Technical content

Features

► 300V breakdown voltage ► Integrated gate-to-source resistor ► Integrated gate-to-source Zener diode ► Low input capacitance ► Fast switching speeds ► Free from secondary breakdown

Applications

► High voltage level translators ► Current sources ► High side switches ► Discrete Amplifier 300V, Dual P-Channel Enhancement-Mode Lateral MOSFET General Description The LP1030D is a dual high voltage P-channel enhancement- mode (normally-off) lateral MOSFET. Each MOSFET has integrated gate-to-source resistor and gate-to-source Zener diode. This allows the device to be easily driven with a capacitively coupled gate drive circuit. The LP1030D utilizes an advanced lateral MOSFET structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally-induced secondary breakdown. Absolute Maximum Ratings Parameter Value Drain-to-source voltage BVDSS Drain-to-gate voltage BVDGS Gate-Source voltage -16V to +1.0V Operating temperature range -25°C to 125°C Absolute Maximum Ratings are those values beyond which damage to the device can occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Pin Configuration 5-Lead SOT-23 (Top View) 5-Lead SOT-23 Package Marking Package may or may not include the following marks: Si or Typical Thermal Resistance Package θja 5-Lead SOT-23 253°C/W Note: Thermal testboard per JEDEC JESD51-7

Ordering Information

Part Number Package Option Packing LP1030DK1-G 5-Lead SOT-23 2500/Reel Product Summary BVDSS (V) RDS(ON) (typ Ω) VGS(th) (max V) ID(ON) (min mA) -300 180 -2.4 -50 S1,2 P0TW W = Code for Week Sealed = “Green” Packaging -G denotes a lead (Pb)-free / RoHS compliant package

Supertex inc. www.supertex.com Doc.# DSFP-LP1030D A031414 Switching Waveforms and Test Circuit 90% 10% 90% 90% 10%10% Pulse Generator VDD RL OUTPUT D.U.T.t(ON) td(ON) t(OFF) td(OFF) tftr INPUT RGEN INPUT OUTPUT VDD -10V Block Diagram P-Channel Electrical Characteristics (Tj = 25°C unless otherwise specified) Sym Parameter Min Typ Max Units Conditions BVDSS Drain-to-source breakdown voltage -300 - - V VGS = 0V, ID = -2.0mA VGS(th) Gate threshold voltage -1.4 -1.7 -2.4 V VGS = VDS, ID = -1.0mA ΔVGS(th) Change in VGS(th) with temperature - - 5.0 mV/°C VGS = VDS, ID = -1.0mA RGS Gate-to-source shunt resistor 15 - 45 kΩ IGS = -100µA VZ Gate-to-source Zener voltage 16 - - V IGS = -1.0mA IDSS Zero gate voltage drain current - - -10 µA VGS = 0V, VDS = Max rating - - -1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125°C ID(ON) On-state drain current -50 - - mA VGS = -7.0V, VDS = -25V RDS(ON) Static drain-to-source on-state resistance - 180 - Ω VGS = -7.0V, ID = -20mA CISS Input capacitance - 10.8 - pF VGS = 0V, VDS = -25V, f = 1.0MHz COSS Common source output capacitance - 4.2 - CRSS Reverse transfer capacitance - 3.1 - td(ON) Turn-on delay time - 1.0 - ns VDD = -25V, ID = -50mA, RGEN = 25Ω tr Rise time - 11.5 - td(OFF) Turn-off delay time - 3.8 - tf Fall time - 16 - VSD Diode forward voltage drop - - -1.8 V VGS = 0V, ISD = -25mA trr Reverse recovery time - 300 - ns VGS = 0V, ISD = -25mA Notes: 2. All A.C. parameters sample tested. S12

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2014 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888 www.supertex.com (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) LP1030D Doc.# DSFP-LP1030D A031414 5-Lead SOT-23 Package Outline (K1) 2.90x1.60mm body, 1.45mm height (max), 0.95mm pitch Symbol A A1 A2 b D E E1 e e1 L L1 L2 θ θ1 Dimension (mm) 0.95 BSC 1.90 BSC 0.30 0.60 REF 0.25 BSC 0O 5O JEDEC Registration MO-178, Variation AA, Issue C, Feb. 2000. * This dimension is not specified in the JEDEC drawing. Drawings not to scale. Supertex Doc. #: DSPD-5SOT23K1, Version A041309. D Seating Plane Gauge Plane L Top View Side View View A - A View B View B θ E1 E A A2 A A Seating Plane e b Note 1 (Index Area D/2 x E/2) Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator.