LP0701LG-G SUTEX | Alldatasheet

Document overview

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Technical content

Features

Freedom from secondary breakdown Low input and output leakage

Applications

General purpose line drivers P-Channel Enhancement-Mode Lateral MOSFET General Description These enhancement-mode (normally-off) transistors utilize a lateral MOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and negative temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally induced secondary breakdown. The low threshold voltage and low on-resistance characteristics are ideally suited for hand held, battery operated applications. Product Marking 8-Lead SOIC (LG) YY = Year Sealed WW = Week Sealed = “Green” Packaging SiLP 0 7 0 1 YYW W TO-92 (N3) YY = Year Sealed WW = Week Sealed L = Lot Number = “Green” Packaging YYWW P0701 L L L L

Ordering Information

Package Options BVDSS/BVDGS (V) RDS(ON) (Ω) VGS(TH) (max) (V) ID(ON) (min) (A)8-Lead SOIC (Narrow Body) TO-92 LP0701 LP0701LG-G LP0701N3-G -16.5 1.5 -1.0 -1.25 -G indicates package is RoHS compliant (‘Green’) Package may or may not include the following marks: Si or Package may or may not include the following marks: Si or

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Thermal Characteristics Package ID (continuous)† (mA) ID (pulsed)† (A) Power Dissipation @TC = 25OC (W) θjc (OC/W) θja (OC/W) IDR (mA) IDRM (A) 8-Lead SOIC -700 -1.25 1.5‡ 83 104‡ -700 -1.25 TO-92 -500 -1.25 1.0 125 170 -500 -1.25 Notes: † ID (continuous) is limited by max rated Tj. ‡ Mounted on FR4 board, 25mm x 25mm x 1.57mm Sym Parameter Min Typ Max Units Conditions BVDSS Drain-to-source breakdown voltage -16.5 - - V VGS = 0V, ID = -1.0mA VGS Gate threshold voltage -0.5 -0.7 -1.0 V VGS = VDS, ID = -1.0mA ΔVGS(th) Change in VGS(th) with temperature - - -4.0 mV/OC VGS = VDS, ID = -1.0mA IGSS Gate body leakage - - -100 nA VGS = ±10V, VDS = 0V IDSS Zero gate voltage drain current - - -100 nA VDS = -15V, VGS = 0V - - -1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125OC ID(ON) On-state drain current - -0.4 - A VGS = VDS = -2.0V RDS(ON) Static drain-to-source on-state resistance - 2.0 4.0 Ω VGS = -2.0V, ID = -50mA ΔRDS(ON) Change in RDS(ON) with temperature - - 0.75 %/OC VGS = -5.0V, ID = -300mA GFS Forward transconductance 500 700 - mmho VGS = -15V, ID = -1.0A CISS Input capacitance - 120 250 pF VGS = 0V, VDS = -15V, f = 1.0MHz COSS Common source output capacitance - 100 125 CRSS Reverse transfer capacitance - 40 60 td(ON) Turn-on delay time - - 20 ns VDD = -15V, ID = -1.25A, RGEN = 25Ω tr Rise time - - 20 td(OFF) Turn-off delay time - - 30 tf Fall time - - 30 VSD Diode forward voltage drop - -1.2 -1.5 V VGS = 0V, ISD = -500mA Notes: All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) All A.C. parameters sample tested. Electrical Characteristics (TA = 25°C unless otherwise specified) 90% 10% 90% 90% 10%10% Pulse Generator VDD RL Output D.U.T. t(ON) td(ON) t(OFF) td(OFF) tftr INPUT INPUT OUTPUT VDD RGEN -10V Switching Waveforms and Test Circuit

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Typical Performance Curves Saturation Characteristics 0 -1 -2 -3 -5-4 Maximum Rated Safe Operating Area -0.1 -100-10-1.0 -0.1 -1.0 -10 -0.01 Thermal Response Characteristics Thermal Resistance (normalized) 1.0 0.8 0.6 0.4 0.2 0.001 100.01 0.1 1.0 Transconductance vs. Drain Current 1.0 0.8 0.6 0.4 0.2 0 -2.0-1.0 Power Dissipation vs. Case Temperature 0 15010050 1257525 TA = -55OC TO-92 (DC ) SO-8 (DC ) TO-92 TO-92/SO-8 (pulsed ) -4V -3V -2V -1V -2.5 -2.0 -1.5 -1.0 -0.5 Output Characteristics -2.5 -2.0 -1.5 -1.0 -0.5 0 -4 -8 - 12 -16 VGS = -5.0V -4V -3V -2V -1V ID (amperes) VDS (volts) GFS (seimens) PD (watts) TC (OC)ID (amperes) VDS (volts) tp (seconds) TO-92 TC = 25V PD = 1.0W SO-8 ID (amperes) VDS (volts) ID (amperes) VGS = -5.0V VDS = -15V TA = 25OC TA = 125OC TC = 25OC

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Typical Performance Curves (cont.) Gate Drive Dynamic Characteristics QG (nanocoulombs) VGS(th) (normalized) RDS(ON) (normalized) V(th) and RDS Variation with Temperature On-Resistance vs. Drain Current BVDSS Variation with Temperature BVDSS (normalized) Transfer Characteristics Capacitance vs. Drain-to-Source Voltage 200 C (picofarads) 0 -5 -10 -15 100 0 -1 -2 -3 -4 - 5 -50 0 50 100 1 50 1.1 0 -3 1.4 1.2 1.0 0.8 0.6 0.4 1.6 1.4 1.2 1.0 0.8 0.6 -10 0 1 2 3 4 5 -50 0 50 100 150 238pF f = 1.0MHz -1 -2 -20V VDS = -15V 0.9 1.0 CISS = 115pF RDS(ON) @ -5V, -300mA TA = 125OC VGS = -2.0V ID (amperes)TJ (OC) RDSS(ON) (ohms) ID (amperes) VGS (volts) VDS = -10V VDS (volts) VGS (volts) CISS COSS CRSS TJ (OC) VGS = -3.0V VGS = -5.0V TA = 25OC TA = -55OC V(th) @ -1.0mA

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Seating Plane Gauge Plane L E D e b A A2 Seating Plane A A Top View Side View View B View B θ Note 1 (Index Area D/2 x E1/2) View A-A h h Note 1 Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1 Dimension (mm) 1.27 BSC 0.25 0.40 1.04 REF 0.25 BSC 0O 5O JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-8SOLGTG, Version I041309. Note: This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator.

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry an d specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2010 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888 www.supertex.com LP0701 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-LP0701 A052109 3-Lead TO-92 Package Outline (N3) Symbol A b c D E E1 e e1 L Dimensions (inches) JEDEC Registration TO-92. * This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc.#: DSPD-3TO92N3, Version E041009. Seating Plane Front View Side View Bottom View E D L e c 1 2 3 b A